
APPENDIX A LIST OF I/O REGISTERS
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-31
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.3
Control Register
(T16A_CCCTL3)
0x5464
(16 bits)
D15–14 CAPBTRG
[1:0]
Capture B trigger select
CAPBTRG[1:0] Trigger edge
0x0 R/W
0x3
0x2
0x1
0x0
↑ and ↓
↓
↑
None
D13–12 TOUTBMD
[1:0]
TOUT B mode select
TOUTBMD[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
cmp B:
↑ or ↓
cmp A:
↑ or ↓
cmp A:
↑, B: ↓
Off
D11–10 –
reserved
–
0 when being read.
D9
TOUTBINV TOUT B invert
1 Invert
0 Normal
0
R/W
D8
CCBMD
T16A_CCB register mode select
1 Capture
0 Comparator
0
R/W
D7–6 CAPATRG
[1:0]
Capture A trigger select
CAPATRG[1:0] Trigger edge
0x0 R/W
0x3
0x2
0x1
0x0
↑ and ↓
↓
↑
None
D5–4 TOUTAMD
[1:0]
TOUT A mode select
TOUTAMD[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
cmp B:
↑ or ↓
cmp A:
↑ or ↓
cmp A:
↑, B: ↓
Off
D3–2 –
reserved
–
0 when being read.
D1
TOUTAINV TOUT A invert
1 Invert
0 Normal
0
R/W
D0
CCAMD
T16A_CCA register mode select
1 Capture
0 Comparator
0
R/W
T16A
Comparator/
Capture Ch.3 A
Data Register
(T16A_CCA3)
0x5466
(16 bits)
D15–0 CCA[15:0] Compare/capture A data
CCA15 = MSB
CCA0 = LSB
0x0 to 0xffff
0x0 R/W
T16A
Comparator/
Capture Ch.3 B
Data Register
(T16A_CCB3)
0x5468
(16 bits)
D15–0 CCB[15:0] Compare/capture B data
CCB15 = MSB
CCB0 = LSB
0x0 to 0xffff
0x0 R/W
T16A
Comparator/
Capture Ch.3
Interrupt Enable
Register
(T16A_IEN3)
0x546a
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIE Capture B overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D4
CAPAOWIE Capture A overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D3
CAPBIE
Capture B interrupt enable
1 Enable
0 Disable
0
R/W
D2
CAPAIE
Capture A interrupt enable
1 Enable
0 Disable
0
R/W
D1
CBIE
Compare B interrupt enable
1 Enable
0 Disable
0
R/W
D0
CAIE
Compare A interrupt enable
1 Enable
0 Disable
0
R/W
T16A
Comparator/
Capture Ch.3
Interrupt Flag
Register
(T16A_IFLG3)
0x546c
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIF Capture B overwrite interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D4
CAPAOWIF Capture A overwrite interrupt flag
0
R/W
D3
CAPBIF
Capture B interrupt flag
0
R/W
D2
CAPAIF
Capture A interrupt flag
0
R/W
D1
CBIF
Compare B interrupt flag
0
R/W
D0
CAIF
Compare A interrupt flag
0
R/W
0xffff84–0xffffd0
S1C17 Core I/O
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Processor ID
Register
(IDIR)
0xffff84
(8 bits)
D7–0 IDIR[7:0]
Processor ID
0x10: S1C17 Core
0x10
R
Debug RAM
Base Register
(DBRAM)
0xffff90
(32 bits)
D31–24 –
Unused (fixed at 0)
0x0
R
D23–0 DBRAM[23:0] Debug RAM base address
0x2fc0
0x2f
c0
R
Debug Control
Register
(DCR)
0xffffa0
(8 bits)
D7
IBE4
Instruction break #4 enable
1 Enable
0 Disable
0
R/W
D6
IBE3
Instruction break #3 enable
1 Enable
0 Disable
0
R/W
D5
IBE2
Instruction break #2 enable
1 Enable
0 Disable
0
R/W
D4
DR
Debug request flag
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
D3
IBE1
Instruction break #1 enable
1 Enable
0 Disable
0
R/W
D2
IBE0
Instruction break #0 enable
1 Enable
0 Disable
0
R/W
D1
SE
Single step enable
1 Enable
0 Disable
0
R/W
D0
DM
Debug mode
1 Debug mode 0 User mode
0
R
Instruction
Break Address
Register 1
(IBAR1)
0xffffb4
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR1[23:0] Instruction break address #1
IBAR123 = MSB
IBAR10 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 2
(IBAR2)
0xffffb8
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR2[23:0] Instruction break address #2
IBAR223 = MSB
IBAR20 = LSB
0x0 to 0xffffff
0x0 R/W