
14 UART
14-10
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
8.1 IrDA Receive Detection Clock (PCLK Division Ratio) Selection
Table 14.
IRCLK[2:0]
Division ratio
0x7
1/128
0x6
1/64
0x5
1/32
0x4
1/16
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
(Default: 0x0)
Note: This clock must be selected as a clock faster than sclk16.
The demodulator circuit treats Low pulses with a width of at least two IrDA receive detection clock
cycles as valid and converts them to 16
× sclk16 cycle width Low pulses. Select a clock to enable
detection of input pulses with a minimum width of 1.41 s.
Serial data transfer control
Data transfer control in IrDA mode is identical to that for normal interfaces. For detailed information on data
format settings and data transfer and interrupt control methods, refer to the preceding sections.
Control Register Details
14.9
9.1 List of UART Registers
Table 14.
Address
Register name
Function
0x4100
UART_ST0
UART Ch.0 Status Register
Indicates transfer, buffer and error statuses.
0x4101
UART_TXD0 UART Ch.0 Transmit Data Register
Transmit data
0x4102
UART_RXD0 UART Ch.0 Receive Data Register
Receive data
0x4103
UART_MOD0 UART Ch.0 Mode Register
Sets transfer data format.
0x4104
UART_CTL0 UART Ch.0 Control Register
Controls data transfer.
0x4105
UART_EXP0 UART Ch.0 Expansion Register
Sets IrDA mode.
0x4106
UART_BR0
UART Ch.0 Baud Rate Register
Sets baud rate.
0x4107
UART_FMD0 UART Ch.0 Fine Mode Register
Sets fine mode.
0x4120
UART_ST1
UART Ch.1 Status Register
Indicates transfer, buffer and error statuses.
0x4121
UART_TXD1 UART Ch.1 Transmit Data Register
Transmit data
0x4122
UART_RXD1 UART Ch.1 Receive Data Register
Receive data
0x4123
UART_MOD1 UART Ch.1 Mode Register
Sets transfer data format.
0x4124
UART_CTL1 UART Ch.1 Control Register
Controls data transfer.
0x4125
UART_EXP1 UART Ch.1 Expansion Register
Sets IrDA mode.
0x4126
UART_BR1
UART Ch.1 Baud Rate Register
Sets baud rate.
0x4127
UART_FMD1 UART Ch.1 Fine Mode Register
Sets fine mode.
0x506c
UART_CLK0 UART Ch.0 Clock Control Register
Selects the baud rate generator clock.
0x506d
UART_CLK1 UART Ch.1 Clock Control Register
Selects the baud rate generator clock.
The UART registers are described in detail below. These are 8-bit registers.
Notes: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
The following UART bits should be set with transfers disabled (RXEN = 0).
- All UART_MODx register bits (STPB, PMD, PREN, CHLN)
- All UART_CTLx register bits other than RXEN (RBFI, TIEN, RIEN, REIEN, TEIEN)
- All UART_EXPx register bits (IRMD, IRCLK[2:0])
- All UART_BRx register bits (BR[7:0])
- All UART_FMDx register bits (FMD[3:0])
- All UART_CLKx register bits (CLKDIV[1:0], CLKSRC[1:0], CLKEN)