
16 I2C MASTER (I2CM)
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
16-9
D10
RXE: Receive Execution Bit
Receives 1 byte of data.
1 (R/W): Data reception start
0 (R/W): Ineffective (default)
Setting RXE to 1 and TXE to 0 starts receiving for 1 byte of data. RXE can be set to 1 for subsequent re-
ception, even if the slave address is being sent or data is being received. RXE is reset to 0 as soon as D6
is loaded to the shift register.
D9
TXE: Transmit Execution Bit
Transmits 1 byte of data.
1 (R/W): Data transmission start
0 (R/W): Ineffective (default)
Transmission is started by setting the transmit data to RTDT[7:0] and writing 1 to TXE. TXE can be
set to 1 for subsequent transmission, even if the slave address or data is being sent. TXE is reset to 0 as
soon as the data set in RTDT[7:0] is transferred to the shift register.
D8
RTACK: Receive/Transmit ACK Bit
When transmitting data
Indicates the response bit status.
1 (R/W): Error (NAK)
0 (R/W): ACK (default)
RTACK becomes 0 when ACK is returned from the slave after 1 byte of data is sent, indicating that the
slave has received the data correctly. If RTACK is 1, the slave device is not operating or the data was
not received correctly.
When receiving data
Sets the response bit sent to the slave.
1 (R/W): Error (NAK)
0 (R/W): ACK (default)
To return an ACK after data has been received, RTACK should be set to 0 before the I2CM module
sends the response bit. To return an NAK, set RTACK to 1.
D[7:0]
RTDT[7:0]: Receive/Transmit Data Bits
When transmitting data
Set the transmit data. (Default: 0x0)
Data transmission is started by setting TXE to 1. If a slave address or data is currently being transmit-
ted, transmission begins once the previous transmission is completed. Serial converted data is output
from the SDA0 pin with MSB leading and bits set to 0 as Low level. A cause of transmit buffer empty
interrupt is generated as soon as the data written to this register is transferred to the shift register, after
which the subsequent transmission data can be written.
When receiving data
The received data can be read out. (Default: 0x0)
Data reception is started by setting RXE to 1. If a slave address is currently being transmitted or data
is currently being received, the new reception starts once the previous data has been transferred. The
RBRDY flag is set and a cause of receive buffer full interrupt generated as soon as reception is com-
pleted and the shift register data is transferred to this register. Data can then be read until the subsequent
data has been received. If the subsequent data is received before this register is read out, the contents
are overwritten by the most recent received data. Serial data input from the SDA0 pin with MSB lead-
ing is converted to parallel, with the High level bit set to 1 and the Low level bit set to 0, then loaded to
this register.