
21 R/F CONVERTER (RFC)
21-12
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
Notes: SREF, SSENA, and SSENB are all ineffective when RFCEN/RFC_CTL register is 0 (converting
operation disabled).
Writing 1 to SSENB does not start oscillation when SMODE[1:0]/RFC_CTL register is 0x1 (AC
oscillation mode for resistive sensors) or 0x2 (DC oscillation mode for capacitive sensors).
When writing 1 to SREF, SSENA, or SSENB to start oscillation, be sure to avoid that more
than one bit are set to 1.
Be sure to reset the interrupt flags in the RFC_IFLG register (EREFIF, ESENAIF, ESENBIF,
OVMCIF, and OVTCIF) before starting oscillation using SREF, SSENA, and SSENB.
RFC Measurement Counter Low and High Registers (RFC_MCL, RFC_MCH)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RFC
Measurement
Counter Low
Register
(RFC_MCL)
0x53a4
(16 bits)
D15–0 MC[15:0]
Measurement counter low-order
16-bit data
0x0–0xffff
0x0 R/W
RFC
Measurement
Counter High
Register
(RFC_MCH)
0x53a6
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 MC[23:16]
Measurement counter high-order
8-bit data
0x0–0xff
0x0 R/W
D[7:0]/RFC_MCH, D[15:0]/RFC_MCL
MC[23:0]: Measurement Counter Bits
Measurement counter data can be read and written to. (Default: 0x0)
Note: The measurement counter must be set from the low-order value (MC[15:0]/RFC_MCL register)
first. The counter may not be set to the correct value if the high-order value (MC[23:16]/RFC_
MCH register) is written first.
RFC Time Base Counter Low and High Registers (RFC_TCL, RFC_TCH)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RFC Time Base
Counter Low
Register
(RFC_TCL)
0x53a8
(16 bits)
D15–0 TC[15:0]
Time base counter low-order 16-
bit data
0x0–0xffff
0x0 R/W
RFC Time Base
Counter High
Register
(RFC_TCH)
0x53aa
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TC[23:16]
Time base counter high-order
8-bit data
0x0–0xff
0x0 R/W
D[7:0]/RFC_TCH, D[15:0]/RFC_TCL
TC[23:0]: Time Base Counter Bits
Time base counter data can be read and written to. (Default: 0x0)
Note: The time base counter must be set from the low-order value (TC[15:0]/RFC_TCL register) first.
The counter may not be set to the correct value if the high-order value (TC[23:16]/RFC_TCH reg-
ister) is written first.
RFC Interrupt Mask Register (RFC_IMSK)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RFC Interrupt
Mask Register
(RFC_IMSK)
0x53ac
(16 bits)
D15–5 –
reserved
–
0 when being read.
D4
OVTCIE
TC overflow error interrupt enable
1 Enable
0 Disable
0
R/W
D3
OVMCIE
MC overflow error interrupt enable 1 Enable
0 Disable
0
R/W
D2
ESENBIE
Sensor B oscillation completion
interrupt enable
1 Enable
0 Disable
0
R/W
D1
ESENAIE
Sensor A oscillation completion
interrupt enable
1 Enable
0 Disable
0
R/W
D0
EREFIE
Reference oscillation completion
interrupt enable
1 Enable
0 Disable
0
R/W
D[15:5]
Reserved