
3 MEMORY MAP, BUS CONTROL
3-2
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
* Handling the eight high-order bits during 32-bit accesses
During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order
bits are ignored. However, the stack operation in an interrupt handling reads/writes 32-bit data that consists of the
PSR value as the high-order 8 bits and the return address as the low order 24 bits.
Number of bus cycles calculation example
Number of bus cycles when the CPU accesses the display RAM area (eight-bit device, set to two access cycles)
by a 16-bit read or write instruction.
2 [cycles]
× 2 [bus accesses] = 4 [CCLK cycles]
Restrictions on Access Size
3.1.1
The modules shown below have a restriction on the access size. Appropriate instructions should be used in pro-
gramming.
Flash memory
The Flash memory allows only 16-bit write instructions for programming. Reading data from the Flash memory
has no such restriction.
Other modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. However, reading for an unnecessary
register may change the peripheral module status and it may cause a problem. Therefore, use the appropriate in-
structions according to the device size.
Restrictions on Instruction Execution Cycles
3.1.2
An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below.
This prolongs the instruction fetch cycle for the number of data area access cycles.
When the S1C17705 executes the instruction stored in the Flash area and accesses data in the Flash area or dis-
play RAM area
When the S1C17705 executes the instruction stored in the internal RAM area and accesses data in the internal
RAM area
Flash Area
3.2
Internal Flash Memory
3.2.1
The 512K-byte area from address 0x8000 to address 0x87fff contains a Flash memory (4K bytes
× 128 sectors) for
storing application programs and data. Address 0x8000 is defined as the vector table base address, therefore a vec-
tor table (see “Vector Table” in the “Interrupt Controller (ITC)” chapter) must be placed from the beginning of the
area. The vector table base address can be modified with the MISC_TTBRL/MISC_TTBRH registers.
The Flash memory can be read in 1 to 5 cycles.
Flash Programming
3.2.2
The S1C17705 supports on-board programming of the Flash memory, it makes it possible to program the Flash
memory with the application programs/data by using the debugger through an ICDmini (S5U1C17001H). Fur-
thermore, the S1C17705 supports self-programming by the application program. The Flash memory can be pro-
grammed in 16-bit units. The Flash memory supports two erase methods, chip erase and sector erase.
For the Flash programming using the debugger, see the “S5U1C17001C Manual” included in the S1C17 Family
C Compiler Package. For the self-programming controlled by the user program, see the “Self-Programming (FLS)
Application Notes” for the S1C17705.
Note: The debugger supports chip erase only and does not allow erasing in sector units.