
10 16-BIT PWM TIMERS (T16A)
10-18
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
T16A Comparator/Capture Ch.x A Data Registers (T16A_CCAx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.x A
Data Register
(T16A_CCAx)
0x5406
0x5426
0x5446
0x5466
(16 bits)
D15–0 CCA[15:0] Compare/capture A data
CCA15 = MSB
CCA0 = LSB
0x0 to 0xffff
0x0 R/W
D[15:0]
CCA[15:0]: Compare/Capture A Data Bits
In comparator mode (CCAMD/ T16A_CCCTLx register = 0)
Set a compare A data, which will be compared with the counter value, through this register.
When CBUFEN/T16A_CTLx register is set to 0, accessing to this register directly read/write from/to
the compare A register.
When CBUFEN is set to 1, accessing to this register read/write from/to the compare A buffer. The buf-
fer contents are loaded into the compare A register when the counter is reset.
The data set is compared with the counter data. When the counter reaches the comparison value set,
the compare A signal is asserted and a cause of compare A interrupt occurs. Furthermore, the TOUT
output waveform changes when TOUTAMD[1:0]/T16A_CCCTLx register or TOUTBMD[1:0]/T16A_
CCCTLx register is set to 0x2 or 0x1. These processes do not affect the counter data and the count up
operation.
In capture mode (CCAMD = 1)
When the counter value is captured at the external trigger signal (CAP0/2/4/6) edge selected using
CAPATRG[1:0]/ T16A_CCCTLx register, the captured value is loaded to this register. At the same time
a capture A interrupt can be generated, thus the captured counter value can be read out in the interrupt
handler.
T16A Comparator/Capture Ch.x B Data Registers (T16A_CCBx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.x B
Data Register
(T16A_CCBx)
0x5408
0x5428
0x5448
0x5468
(16 bits)
D15–0 CCB[15:0] Compare/capture B data
CCB15 = MSB
CCB0 = LSB
0x0 to 0xffff
0x0 R/W
D[15:0]
CCB[15:0]: Compare/Capture B Data Bits
In comparator mode (CCBMD/ T16A_CCCTLx register = 0)
Set a compare B data, which will be compared with the counter value, through this register.
When CBUFEN/T16A_CTLx register is set to 0, accessing to this register directly read/write from/to
the compare B register.
When CBUFEN is set to 1, accessing to this register read/write from/to the compare B buffer. The buf-
fer contents are loaded into the compare B register when the counter is reset.
The data set is compared with the counter data. When the counter reaches the comparison value set,
the compare B signal is asserted and a cause of compare B interrupt occurs. The counter is reset to 0.
Furthermore, the TOUT output waveform changes when TOUTAMD[1:0]/T16A_CCCTLx register or
TOUTBMD[1:0]/T16A_CCCTLx register is set to 0x3 or 0x1.
In capture mode (CCBMD = 1)
When the counter value is captured at the external trigger signal (CAP1/3/5/7) edge selected using
CAPBTRG[1:0]/ T16A_CCCTLx register, the captured value is loaded to this register. At the same time
a capture B interrupt can be generated, thus the captured counter value can be read out in the interrupt
handler.