
APPENDIX A LIST OF I/O REGISTERS
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-23
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FLASHC/
SRAMC Control
Register
(MISC_FL)
0x5320
(16 bits)
D15–13 –
reserved
–
0 when being read.
D12
SRRVS
SRAMC bit order reverse
1 Reverse
0 Normal
0
R/W
D11–10 –
reserved
–
0 when being read.
D9–8 SRCYC[1:0] SRAMC access cycle
SRCYC[1:0]
Access cycle
0x3 R/W
0x3
0x2
0x1
0x0
5 cycles
4 cycles
3 cycles
2 cycles
D7–3 –
reserved
–
0 when being read.
D2–0 FLCYC[2:0] FLASHC read access cycle
FLCYC[2:0]
Read cycle
0x3 R/W
0x7–0x5
0x4
0x3
0x2
0x1
0x0
reserved
1 cycle
5 cycles
4 cycles
3 cycles
2 cycles
OSC1 Peripheral
Control Register
(MISC_OSC1)
0x5322
(16 bits)
D15–1 –
reserved
–
0 when being read.
D0
O1DBG
OSC1 peripheral control in debug
mode
1 Run
0 Stop
0
R/W
MISC Protect
Register
(MISC_PROT)
0x5324
(16 bits)
D15–0 PROT[15:0] MISC register write protect
Writing 0x96 removes the write
protection of the MISC regis-
ters (0x5326–0x532a).
Writing another value set the
write protection.
0x0 R/W
IRAM Size
Select Register
(MISC_IRAMSZ)
0x5326
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
DBADR
Debug base address select
1 0x0
0 0xfffc00
0
R/W
D7–2 –
reserved
–
0 when being read.
D1–0 IRAMSZ[1:0] IRAM size select
IRAMSZ[1:0]
Size
0x0 R/W
0x3
0x2
0x1
0x0
2KB
4KB
8KB
12KB
Vector Table
Address Low
Register
(MISC_TTBRL)
0x5328
(16 bits)
D15–8 TTBR[15:8] Vector table base address A[15:8]
0x0–0xff
0x80 R/W
D7–0 TTBR[7:0]
Vector table base address A[7:0]
(fixed at 0)
0x0
R
Vector Table
Address High
Register
(MISC_TTBRH)
0x532a
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TTBR[23:16] Vector table base address
A[23:16]
0x0–0xff
0x0 R/W
PSR Register
(MISC_PSR)
0x532c
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–5 PSRIL[2:0] PSR interrupt level (IL) bits
0x0 to 0x7
0x0
R
D4
PSRIE
PSR interrupt enable (IE) bit
1 1 (enable)
0 0 (disable)
0
R
D3
PSRC
PSR carry (C) flag
1 1 (set)
0 0 (cleared)
0
R
D2
PSRV
PSR overflow (V) flag
1 1 (set)
0 0 (cleared)
0
R
D1
PSRZ
PSR zero (Z) flag
1 1 (set)
0 0 (cleared)
0
R
D0
PSRN
PSR negative (N) flag
1 1 (set)
0 0 (cleared)
0
R
0x5340–0x5346
IR Remote Controller
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
REMC
Configuration
Register
(REMC_CFG)
0x5340
(16 bits)
D15–12 CGCLK[3:0] Carrier generator clock division
ratio select
CGCLK[3:0]
LCCLK[3:0]
Division ratio
0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D11–8 LCCLK[3:0] Length counter clock division ratio
select
0x0 R/W
D7–2 –
reserved
–
0 when being read.
D1
REMMD
REMC mode select
1 Receive
0 Transmit
0
R/W
D0
REMEN
REMC enable
1 Enable
0 Disable
0
R/W
REMC Carrier
Length Setup
Register
(REMC_CAR)
0x5342
(16 bits)
D15–14 –
reserved
–
0 when being read.
D13–8 REMCL[5:0] Carrier L length setup
0x0 to 0x3f
0x0 R/W
D7–6 –
reserved
–
0 when being read.
D5–0 REMCH[5:0] Carrier H length setup
0x0 to 0x3f
0x0 R/W