
16 I2C MASTER (I2CM)
16-2
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S1C17705 TECHNICAL MANUAL
Synchronization Clock
16.3
The I2CM module uses the internal clock (I2CM clock) output by the 16-bit timer (T16) Ch.3 as the synchroniza-
tion clock. This clock is output from the SCL0 pin to the slave device while also driving the shift register. The clock
should be programmed to output a signal matching the transfer rate from T16 Ch.3. For more information on T16
control, see the “16-bit Timers (T16)” chapter.
The I2CM module does not function as a slave device. The SCL0 input pin is used to check the I2C bus SCL signal
status. It is not used for synchronization clock input.
Settings Before Data Transfer
16.4
The I2CM module includes an optional noise filter function that can be selected via the application program.
Noise filter function
The I2CM module includes a function for filtering noise from the SDA0 and SCL0 pin input signals. This
function is enabled by setting NSERM/I2CM_CTL register to 1. Note that using this function requires setting
the I2CM clock (T16 Ch.3 output clock) frequency to 1/6 or less of PCLK.
Data Transfer Control
16.5
Make the following settings before starting data transfers.
(1) Configure T16 Ch.3 to output the I2CM clock. (See the T16 module chapter.)
(2) Select the option function. (See Section 16.4.)
(3) Set the interrupt conditions to use I2CM interrupts. (See Section 16.6.)
Note: Make sure the I2CM module is halted (I2CMEN/I2CM_EN register = 0) before changing the above
settings.
Enabling data transfers
Set I2CMEN/I2CM_EN register to 1 to enable I2CM operations. This enables I2CM transfers and clock input/
output.
Note: Do not set I2CMEN to 0 when the I2CM module is transferring data.
Starting Data transfer
To start data transfers, the I2C master (this module) must generate a start condition. The slave address is then
sent to establish communications.
(1) Generating start condition
The start condition applies when the SCL line is maintained at High and the SDA line is pulled down to Low.
SDA0 (output)
SCL0 (output)
Start condition
5.1 Start Condition
Figure 16.
The start condition is generated by setting STRT/I2CM_CTL register to 1.
STRT is automatically reset to 0 once the start condition is generated. The I2C bus is busy from this point on.
(2) Slave address transmission
Once the start condition has been generated, the I2C master (this module) sends a bit indicating the slave address
and transfer direction for communications. I2C slave addresses are either 7-bit or 10-bit. This module uses an
8-bit transfer data register to send the slave address and transfer direction bit, enabling single transfers in 7-bit
address mode. In 10-bit mode, data is sent twice under software control. Figure 16.5.2 shows the configuration
of the address data.