
14 UART
14-12
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
D2
TRBS: Transmit Busy Flag Bit
Indicates the transmit shift register status.
1 (R):
Operating
0 (R):
Standby (default)
TRBS is set to 1 when transmit data is loaded from the transmit data buffer into the shift register and is
reset to 0 when the data transfer is completed. Inspect TRBS to determine whether the transmit circuit
is operating or at standby.
D1
RDRY: Receive Data Ready Flag Bit
Indicates that the receive data buffer contains valid received data.
1 (R):
Data can be read
0 (R):
Buffer empty (default)
RDRY is set to 1 when received data is loaded into the receive data buffer and is reset to 0 when all data
has been read from the receive data buffer.
D0
TDBE: Transmit Data Buffer Empty Flag Bit
Indicates the transmit data buffer status.
1 (R):
Buffer empty (default)
0 (R):
Data exists
TDBE is reset to 0 when transmit data is written to the transmit data buffer and is set to 1 when the data
is transferred to the shift register.
UART Ch.x Transmit Data Registers (UART_TXDx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Transmit Data
Register
(UART_TXDx)
0x4101
0x4121
(8 bits)
D7–0 TXD[7:0]
Transmit data
TXD7(6) = MSB
TXD0 = LSB
0x0 to 0xff (0x7f)
0x0 R/W
D[7:0]
TXD[7:0]: Transmit Data
Write transmit data to be set in the transmit data buffer. (Default: 0x0)
The UART starts transmitting when data is written to this register. Data written to TXD[7:0] is retained
until sent to the transmit data buffer. Transmitting data from within the transmit data buffer generates a
cause of transmit buffer empty interrupt.
TXD7 (MSB) is invalid in 7-bit mode.
Serial converted data is output from the SOUTx pin beginning with the LSB, in which the bits set to 1
are output as High level and bits set to 0 as Low level signals.
This register can also be read.
UART Ch.x Receive Data Registers (UART_RXDx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Receive Data
Register
(UART_RXDx)
0x4102
0x4122
(8 bits)
D7–0 RXD[7:0]
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
0x0 to 0xff (0x7f)
0x0
R Older data in the buf-
fer is read out first.
D[7:0]
RXD[7:0]: Receive Data
Data in the receive data buffer is read out in sequence, starting with the oldest. Received data is placed in
the receive data buffer. The receive data buffer is a 2-byte FIFO that allows proper data reception until it
fills, even if data is not read out. If the buffer is full and the shift register also contains received data, an
overrun error will occur, unless the data is read out before reception of the subsequent data starts.
The receive circuit includes two receive buffer status flags: RDRY/UART_STx register and RD2B/
UART_STx register. The RDRY flag indicates the presence of valid received data in the receive data
buffer, while the RD2B flag indicates the presence of two received data in the receive data buffer.
A receive buffer full interrupt occurs when the received data in the receive data buffer reaches the num-
ber specified by RBFI/UART_CTLx register.