
19 LCD DRIVER (LCD)
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
19-17
LCD Interrupt
19.8
The LCD module includes a function for generating interrupts using the frame signal.
Frame interrupt
This cause of interrupt occurs every frame and sets the interrupt flag FRMIF/LCD_IFLG register in the LCD
module to 1. See Figures 19.5.2.1 to 19.5.2.3 for interrupt timings.
To use this interrupt, set FRMIE/LCD_IMSK register to 1. When FRMIE is set to 0 (default), interrupt requests
for this interrupt cause are not sent to the interrupt controller (ITC).
If FRMIF is set to 1 while FRMIE is set to 1 (interrupt enabled), the LCD module outputs an interrupt request
to the ITC. An interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Notes: To prevent interrupt recurrences, the LCD module interrupt flag FRMIF must be reset in the
interrupt handler routine after an LCD interrupt has occurred.
To prevent unwanted interrupts, FRMIF should be reset before enabling LCD interrupts with
FRMIE.
Control Register Details
19.9
9.1 List of LCD Registers
Table 19.
Address
Register name
Function
0x5063
LCD_CLK
LCD Clock Select Register
Selects the LCD clock.
0x50a0
LCD_DCTL
LCD Display Control Register
Controls the LCD display.
0x50a1
LCD_CADJ
LCD Contrast Adjustment Register
Controls the contrast.
0x50a2
LCD_CCTL
LCD Clock Control Register
Controls the LCD drive duty.
0x50a3
LCD_VREG
LCD Voltage Regulator Control Register
Controls the LCD drive voltage regulator.
0x50a4
LCD_PWR
LCD Power Voltage Booster Control Register
Controls the LCD voltage booster.
0x50a5
LCD_IMSK
LCD Interrupt Mask Register
Enables/disables interrupts.
0x50a6
LCD_IFLG
LCD Interrupt Flag Register
Indicates/resets interrupt occurrence status.
The LCD module registers are described in detail below. These are 8-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
LCD Clock Select Register (LCD_CLK)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
LCD Clock
Select Register
(LCD_CLK)
0x5063
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 LCKDV[2:0] LCD clock division ratio select
LCKDV[2:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x7–0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/512
1/256
1/128
1/64
1/32
D[3:2] LCKSRC
[1:0]
LCD clock source select
LCKSRC[1:0]
Clock source
0x1 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
D1
–
reserved
–
0 when being read.
D0
LCKEN
LCD clock enable
1 Enable
0 Disable
0
R/W
D7
Reserved
D[6:4]
LCKDV[2:0]: LCD Clock Division Ratio Select Bits
Select the division ratio when IOSC or OSC3 is selected as the LCD clock source.