
APPENDIX A LIST OF I/O REGISTERS
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-25
0x5067, 0x53a0–0x53ae
R/F Converter
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RFC Clock
Control Register
(RFC_CLK)
0x5067
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 CLKDIV
[1:0]
RFC clock division ratio select
CLKDIV[1:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x3
0x2
0x1
0x0
1/8
1/4
1/2
1/1
D3–2 CLKSRC
[1:0]
RFC clock source select
CLKSRC[1:0]
Clock source
0x1 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
D1
–
reserved
–
0 when being read.
D0
CLKEN
RFC clock enable
1 Enable
0 Disable
0
R/W
RFC Control
Register
(RFC_CTL)
0x53a0
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
CONEN
Continuous oscillation enable
1 Enable
0 Disable
0
R/W
D6
EVTEN
Event counter mode enable
1 Enable
0 Disable
0
R/W
D5–4 SMODE[1:0] Sensor oscillation mode select
SMODE[1:0]
Sensor
0x0 R/W
0x3
0x2
0x1
0x0
reserved
DC capacitive
AC resistive
DC resistive
D3–2 –
reserved
–
0 when being read.
D1
CHSEL
Conversion channel select
1 Ch.1
0 Ch.0
0
R/W
D0
RFCEN
RFC enable
1 Enable
0 Disable
0
R/W
RFC Oscillation
Trigger Register
(RFC_TRG)
0x53a2
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
SSENB
Sensor B oscillation control/status
1 Start/Run
0 Stop
0
R/W
D1
SSENA
Sensor A oscillation control/status
1 Start/Run
0 Stop
0
R/W
D0
SREF
Reference oscillation control/status 1 Start/Run
0 Stop
0
R/W
RFC
Measurement
Counter Low
Register
(RFC_MCL)
0x53a4
(16 bits)
D15–0 MC[15:0]
Measurement counter low-order
16-bit data
0x0–0xffff
0x0 R/W
RFC
Measurement
Counter High
Register
(RFC_MCH)
0x53a6
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 MC[23:16]
Measurement counter high-order
8-bit data
0x0–0xff
0x0 R/W
RFC Time Base
Counter Low
Register
(RFC_TCL)
0x53a8
(16 bits)
D15–0 TC[15:0]
Time base counter low-order 16-
bit data
0x0–0xffff
0x0 R/W
RFC Time Base
Counter High
Register
(RFC_TCH)
0x53aa
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TC[23:16]
Time base counter high-order
8-bit data
0x0–0xff
0x0 R/W
RFC Interrupt
Mask Register
(RFC_IMSK)
0x53ac
(16 bits)
D15–5 –
reserved
–
0 when being read.
D4
OVTCIE
TC overflow error interrupt enable
1 Enable
0 Disable
0
R/W
D3
OVMCIE
MC overflow error interrupt enable 1 Enable
0 Disable
0
R/W
D2
ESENBIE
Sensor B oscillation completion
interrupt enable
1 Enable
0 Disable
0
R/W
D1
ESENAIE
Sensor A oscillation completion
interrupt enable
1 Enable
0 Disable
0
R/W
D0
EREFIE
Reference oscillation completion
interrupt enable
1 Enable
0 Disable
0
R/W
RFC Interrupt
Flag Register
(RFC_IFLG)
0x53ae
(16 bits)
D15–5 –
reserved
–
0 when being read.
D4
OVTCIF
TC overflow error interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D3
OVMCIF
MC overflow error interrupt flag
0
R/W
D2
ESENBIF
Sensor B oscillation completion
interrupt flag
0
R/W
D1
ESENAIF
Sensor A oscillation completion
interrupt flag
0
R/W
D0
EREFIF
Reference oscillation completion
interrupt flag
0
R/W