
6 INTERRUPT CONTROLLER (ITC)
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
6-7
D[15:11] Reserved
D[10:8]
ILV1[2:0]: P1 Interrupt Level Bits
Set the P1 port interrupt level (0 to 7). (Default: 0x0)
The S1C17 Core does not accept interrupts with a level set lower than the PSR IL value.
The ITC uses the interrupt level when multiple interrupt requests occur simultaneously.
If multiple interrupt requests enabled by the interrupt enable bit occur simultaneously, the ITC sends the
interrupt request with the highest level set by the ITC_LVx registers (0x4306 to 0x431c) to the S1C17
Core.
If multiple interrupt requests with the same interrupt level occur simultaneously, the interrupt with the
lowest vector number is processed first.
The other interrupts are held until all interrupts of higher priority have been accepted by the S1C17
Core.
If an interrupt requests of higher priority occurs while the ITC outputs an interrupt request signal to the
S1C17 Core (before acceptance by the S1C17 Core), the ITC alters the vector number and interrupt
level signals to the setting details of the most recent interrupt. The immediately preceding interrupt is
held.
D[7:3]
Reserved
D[2:0]
ILV0[2:0]: P0 Interrupt Level Bits
Set the P0 port interrupt level (0 to 7). (Default: 0x0)
See the description of ILV1[2:0].
Interrupt Level Setup Register 1 (ITC_LV1)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Interrupt Level
Setup Register 1
(ITC_LV1)
0x4308
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV3[2:0]
CT interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV2[2:0]
SWT interrupt level
0 to 7
0x0 R/W
D[15:11] Reserved
D[10:8]
ILV3[2:0]: CT Interrupt Level Bits
Set the clock timer interrupt level (0 to 7). (Default: 0x0)
See the description of ILV1[2:0]/ITC_LV0 register.
D[7:3]
Reserved
D[2:0]
ILV2[2:0]: SWT Interrupt Level Bits
Set the stopwatch timer interrupt level (0 to 7). (Default: 0x0)
See the description of ILV1[2:0]/ITC_LV0 register.
Interrupt Level Setup Register 2 (ITC_LV2)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Interrupt Level
Setup Register 2
(ITC_LV2)
0x430a
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV5[2:0]
SVD interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV4[2:0]
T16A Ch.2 interrupt level
0 to 7
0x0 R/W
D[15:11] Reserved
D[10:8]
ILV5[2:0]: SVD Interrupt Level Bits
Set the SVD interrupt level (0 to 7). (Default: 0x0)
See the description of ILV1[2:0]/ITC_LV0 register.
D[7:3]
Reserved
D[2:0]
ILV4[2:0]: T16A Ch.2 Interrupt Level Bits
Set the 16-bit PWM timer Ch.2 interrupt level (0 to 7). (Default: 0x0)
See the description of ILV1[2:0]/ITC_LV0 register.