
APPENDIX A LIST OF I/O REGISTERS
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-13
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SPI Ch.2
Control Register
(SPI_CTL2)
0x43a6
(16 bits)
D15–10 –
reserved
–
0 when being read.
D9
MCLK
SPI clock source select
1 T16 Ch.2
0 PCLK/4
0
R/W
D8
MLSB
LSB/MSB first mode select
1 LSB
0 MSB
0
R/W
D7–6 –
reserved
–
0 when being read.
D5
SPRIE
Receive data buffer full int. enable 1 Enable
0 Disable
0
R/W
D4
SPTIE
Transmit data buffer empty int. enable 1 Enable
0 Disable
0
R/W
D3
CPHA
Clock phase select
1 Data out
0 Data in
0
R/W These bits must be
set before setting
SPEN to 1.
D2
CPOL
Clock polarity select
1 Active L
0 Active H
0
R/W
D1
MSSL
Master/slave mode select
1 Master
0 Slave
0
R/W
D0
SPEN
SPI enable
1 Enable
0 Disable
0
R/W
0x5000–0x5003
Clock Timer
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Clock Timer
Control Register
(CT_CTL)
0x5000
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
CTRST
Clock timer reset
1 Reset
0 Ignored
0
W
D3–1 –
reserved
–
D0
CTRUN
Clock timer run/stop control
1 Run
0 Stop
0
R/W
Clock Timer
Counter Register
(CT_CNT)
0x5001
(8 bits)
D7–0 CTCNT[7:0] Clock timer counter value
0x0 to 0xff
0
R
Clock Timer
Interrupt Mask
Register
(CT_IMSK)
0x5002
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
CTIE32
32 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D2
CTIE8
8 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D1
CTIE2
2 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D0
CTIE1
1 Hz interrupt enable
1 Enable
0 Disable
0
R/W
Clock Timer
Interrupt Flag
Register
(CT_IFLG)
0x5003
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
CTIF32
32 Hz interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D2
CTIF8
8 Hz interrupt flag
0
R/W
D1
CTIF2
2 Hz interrupt flag
0
R/W
D0
CTIF1
1 Hz interrupt flag
0
R/W
0x5020–0x5023
Stopwatch Timer
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Stopwatch
Timer Control
Register
(SWT_CTL)
0x5020
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
SWTRST
Stopwatch timer reset
1 Reset
0 Ignored
0
W
D3–1 –
reserved
–
D0
SWTRUN
Stopwatch timer run/stop control
1 Run
0 Stop
0
R/W
Stopwatch
Timer BCD
Counter Register
(SWT_BCNT)
0x5021
(8 bits)
D7–4 BCD10[3:0] 1/10 sec. BCD counter value
0 to 9
0
R
D3–0 BCD100[3:0] 1/100 sec. BCD counter value
0 to 9
0
R
Stopwatch
Timer Interrupt
Mask Register
(SWT_IMSK)
0x5022
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SIE1
1 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D1
SIE10
10 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D0
SIE100
100 Hz interrupt enable
1 Enable
0 Disable
0
R/W
Stopwatch
Timer Interrupt
Flag Register
(SWT_IFLG)
0x5023
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SIF1
1 Hz interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D1
SIF10
10 Hz interrupt flag
0
R/W
D0
SIF100
100 Hz interrupt flag
0
R/W
0x5040–0x5041
Watchdog Timer
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Watchdog
Timer Control
Register
(WDT_CTL)
0x5040
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
WDTRST
Watchdog timer reset
1 Reset
0 Ignored
0
W
D3–0 WDTRUN[3:0] Watchdog timer run/stop control
Other than 1010
Run
1010
Stop
1010 R/W
Watchdog
Timer Status
Register
(WDT_ST)
0x5041
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
WDTMD
NMI/Reset mode select
1 Reset
0 NMI
0
R/W
D0
WDTST
NMI status
1 NMI occurred 0 Not occurred
0
R