
15 SPI
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
15-5
PCLK
SPEN
SPI clock (master mode)
SPI_TXDx register
SPICLKx pin
(CPOL = 0, CPHA = 1)
SPICLKx pin
(CPOL = 0, CPHA = 0)
SDIx pin
Shift register
SPI_RXDx register
SPBSY
SPRBF
Interrupt
Data A
Data B
AD7
BD7
AD6
AD0
BD0
Write
Read
dummy
BD6
5.2 Data Receiving Timing Chart (MSB first)
Figure 15.
Disabling data transfers
After a data transfer is completed (both transmission and reception), write 0 to SPEN to disable data transfers.
Confirm that the SPTBE flag is 1 and the SPRBF flag is 0 before disabling data transfer.
Setting SPEN to 0 empties the transmit and receive data buffers, clearing any remaining data. The data being
transferred cannot be guaranteed if SPEN is set to 0 while data is being sent or received.
SPI Interrupts
15.6
Each channel of the SPI module includes a function for generating the following two different types of interrupts.
Transmit buffer empty interrupt
Receive buffer full interrupt
The SPI channel outputs one interrupt signal shared by the two above interrupt causes to the interrupt controller (ITC).
Inspect the status flag to determine the interrupt cause occurred.
Transmit buffer empty interrupt
To use this interrupt, set SPTIE/SPI_CTLx register to 1. If SPTIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
When transmit data written to the transmit data buffer is transferred to the shift register, the SPI module sets
SPTBE/SPI_STx register to 1, indicating that the transmit data buffer is empty. If transmit buffer empty inter-
rupts are enabled (SPTIE = 1), an interrupt request is sent simultaneously to the ITC.
An interrupt occurs if other interrupt conditions are met. You can inspect the SPTBE flag in the SPI interrupt
handler routine to determine whether the SPI interrupt is attributable to a transmit buffer empty. If SPTBE is 0,
the next transmit data can be written to the transmit data buffer by the interrupt handler routine.
Receive buffer full interrupt
To use this interrupt, set SPRIE/SPI_CTLx register to 1. If SPRIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
When data received in the shift register is loaded into the receive data buffer, the SPI module sets SPRBF/SPI_
STx register to 1, indicating that the receive data buffer contains readable received data. If receive buffer full
interrupts are enabled (SPRIE = 1), an interrupt request is output to the ITC at the same time.
An interrupt occurs if other interrupt conditions are met. You can inspect the SPRBF flag in the SPI interrupt
handler routine to determine whether the SPI interrupt is attributable to a receive buffer full. If SPRBF is 1, the
received data can be read from the receive data buffer by the interrupt handler routine.
For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.