
APPENDIX A LIST OF I/O REGISTERS
AP-A-16
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SVD
Comparison
Voltage Register
(SVD_CMP)
0x5101
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–0 SVDC[3:0] SVD comparison voltage select
SVDC[3:0]
Voltage
0x0 R/W
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
1.9 V
1.8 V
reserved
SVD Detection
Result Register
(SVD_RSLT)
0x5102
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
SVDDT
SVD detection result
1 Low
0 Normal
×
R
SVD Interrupt
Mask Register
(SVD_IMSK)
0x5103
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
SVDIE
SVD interrupt enable
1 Enable
0 Disable
0
R/W
SVD Interrupt
Flag Register
(SVD_IFLG)
0x5104
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
SVDIF
SVD interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
0x5120–0x5122
Power Generator
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
VD1 Control
Register
(VD1_CTL)
0x5120
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
HVLD
VD1 heavy load protection mode
1 On
0 Off
0
R/W
D4–1 –
reserved
–
0 when being read.
D0
VD1MD
Flash erase/programming mode
1 Flash (2.5 V) 0 Norm.(1.8 V)
0
R/W
VD1 Select
Register
(VD1_SEL)
0x5122
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
VD1SEL
VD1 regulator output level select
1 VDD level
0 Normal level
0
R/W
0x5200–0x52a8
P Port & Port MUX
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port Input
Data Register
(P0_IN)
0x5200
(8 bits)
D7–0 P0IN[7:0]
P0[7:0] port input data
1 1 (H)
0 0 (L)
×
R
P0 Port Output
Data Register
(P0_OUT)
0x5201
(8 bits)
D7–0 P0OUT[7:0] P0[7:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P0 Port
Output Enable
Register
(P0_OEN)
0x5202
(8 bits)
D7–0 P0OEN[7:0] P0[7:0] port output enable
1 Enable
0 Disable
0
R/W
P0 Port Pull-up
Control Register
(P0_PU)
0x5203
(8 bits)
D7–0 P0PU[7:0]
P0[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
P0 Port Schmitt
Trigger Control
Register
(P0_SM)
0x5204
(8 bits)
D7–0 P0SM[7:0] P0[7:0] port Schmitt trigger input
enable
1 Enable
(Schmitt)
0 Disable
(CMOS)
1
(0xff)
R/W
P0 Port
Interrupt Mask
Register
(P0_IMSK)
0x5205
(8 bits)
D7–0 P0IE[7:0]
P0[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P0 Port
Interrupt Edge
Select Register
(P0_EDGE)
0x5206
(8 bits)
D7–0 P0EDGE[7:0] P0[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P0 Port
Interrupt Flag
Register
(P0_IFLG)
0x5207
(8 bits)
D7–0 P0IF[7:0]
P0[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.