Advance Information Page 80 of 114 JUNE 2008 REVISION 1.1 14.1.10 HEADER TYPE REGISTER – OFFSET" />
參數(shù)資料
型號: PI7C8154BNAIE
廠商: Pericom
文件頁數(shù): 94/114頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 80 of 114
JUNE 2008 REVISION 1.1
14.1.10
HEADER TYPE REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
23:16
Header Type
R/O
Read as 01h to indicate that the register layout conforms to the standard
PCI-to-PCI bridge layout.
14.1.11
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
7:0
Primary Bus
Number
R/W
Indicates the number of the PCI bus to which the primary interface is
connected. The value is set in software during configuration.
Reset to 0
14.1.12
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
15:8
Secondary Bus
Number
R/W
Indicates the number of the PCI bus to which the secondary interface is
connected. The value is set in software during configuration.
Reset to 0
14.1.13
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
23:16
Subordinate Bus
Number
R/W
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
14.1.14
SECONDARY LATENCY TIMER – OFFSET 18h
Bit
Function
Type
Description
31:24
Secondary
Latency Timer
R/W
Designated in units of PCI bus clocks. Latency timer checks for master
accesses on the secondary bus interfaces that remain unclaimed by any
target.
Reset to 0
14.1.15
I/O BASE REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
1:0
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
3:2
Reserved
R/O
Returns 00 when read. Reset to 00.
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