Advance Information Page 92 of 114 JUNE 2008 REVISION 1.1 14.1.44 GPIO DATA AND CONTROL REGISTE" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 107/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 92 of 114
JUNE 2008 REVISION 1.1
14.1.44
GPIO DATA AND CONTROL REGISTER – OFFSET 64h
Bit
Function
Type
Description
11:8
GPIO output
write-1-to-clear
R/WC
Setting any of these bits to 1 drives the corresponding bits LOW on the
GPIO[3:0] bus if it is programmed as bi-directional. Data is driven on the
PCI clock cycle following completion of the configuration write to this
register. The bit positions corresponding to the GPIO pins that are
programmed as input only are not driven. Writing 0 to theses bits has no
effect and will return the last written value when read. Bits [11:8]
correspond to GPIO [3:0].
Reset to 0
15:12
GPIO output
write-1-to-set
R/WS
Setting any of these bits to 1 drives the corresponding bits HIGH on the
GPIO[3:0] bus if it is programmed as bi-directional. Data is driven on the
PCI clock cycle following completion of the configuration write to this
register. The bit positions corresponding to the GPIO pins that are
programmed as input only are not driven. Writing 0 to theses bits has no
effect and will return the last written value when read. Bits [15:12]
correspond to GPIO [3:0].
Reset to 0
19:16
GPIO output
enable write-1-
to-clear
R/WC
Setting any of these bits to 1 configures the corresponding bits on the
GPIO[3:0] bus as input only. As a result, the output driver is tri-stated.
Writing 0 to theses bits has no effect and will return the last written value
when read. Bits [19:16] correspond to GPIO [3:0].
Reset to 0
23:20
GPIO output
enable write-1-
to-set
R/WS
Setting any of these bits to 1 configures the corresponding bits on the
GPIO[3:0] bus as bi-directional; the output driver is enabled and drives
the value set in the output data register (offset 65h). Writing 0 to theses
bits has no effect and will return the last written value when read. Bits
[23:20] correspond to GPIO [3:0].
Reset to 0
27:24
Reserved
R/O
Returns 0 when read. Reset to 0
31:28
GPIO Input Data
Register
R/O
Contains the state of the GPIO[3:0] pins. State is updated on the PCI
clock cycle after any change to the state of the GPIO[3:0] pins.
Reset to 0.
14.1.45
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
Function
Type
Description
1:0
S_CLKOUT[0]
disable
R/W
S_CLKOUT[0] (slot 0) Enable
00: enable S_CLKOUT[0]
01: enable S_CLKOUT[0]
10: enable S_CLKOUT[0]
11: disable S_CLKOUT[0] and driven HIGH
Reset to 00
3:2
S_CLKOUT[1]
disable
R/W
S_CLKOUT[1] (slot 1) Enable
00: enable S_CLKOUT[1]
01: enable S_CLKOUT[1]
10: enable S_CLKOUT[1]
11: disable S_CLKOUT[1] and driven HIGH
Reset to 00
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