Advance Information Page 91 of 114 JUNE 2008 REVISION 1.1 Bit Function Type Description 1 Poste" />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 106/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 91 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
1
Posted Write
with Parity Error
R/W
0: P_SERR# is asserted if a parity error is detected on the target bus
during a posted write transaction and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted, although a parity error is detected on the
target bus during a posted write transaction and the SERR# enable bit in
the command register is set.
Reset to 0
2
Posted Write
with Non-
Delivery Data
R/W
0: P_SERR# is asserted if the bridge is not able to transfer any posted
write data after 224 attempts and the SERR# enable bit in the command
register is set.
1: P_SERR# is not asserted although the bridge is not able to transfer any
posted write data after 224 attempts and the SERR# enable bit in the
command register is set.
Reset to 0
3
Target Abort
During Posted
Write
R/W
0: P_SERR# is asserted if the bridge receives a target abort when
attempting to deliver posted write data and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge receives a target
abort when attempting to deliver posted write data and the SERR# enable
bit in the command register is set.
Reset to 0
4
Master Abort
During Posted
Write
R/W
0: P_SERR# is asserted if the bridge receives a master abort when
attempting to deliver posted write data and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge receives a master
abort when attempting to deliver posted write data and the SERR# enable
bit in the command register is set.
Reset to 0
5
Delayed Write
with Non-
Delivery
R/W
0: P_SERR# is asserted if the bridge is not able to transfer any delayed
write data after 224 attempts and the SERR# enable bit in the command
register is set.
1: P_SERR# is not asserted even though the bridge is not able to transfer
any delayed write data after 224 attempts and the SERR# enable bit in the
command register is set.
Reset to 0
6
Delayed Read
Without Data
From Target
R/W
0: P_SERR# is asserted if the bridge is not able to transfer any read data
from the target after 224 attempts and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge is not able to transfer
and read data from the target after 224 attempts and the SERR# enable bit
in the command register is set.
Reset to 0.
7
Reserved
R/O
Returns 0 when read. Reset to 0.
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