- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154BNAIE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 66/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當(dāng)前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 55 of 114
JUNE 2008 REVISION 1.1
For upstream transactions, when PI7C8154B detects a read data parity error on the primary bus, the
following events occur:
PI7C8154B asserts P_PERR# 2 cycles following the data transfer, if the primary interface
parity error response bit is set in the command register.
PI7C8154B sets the detected parity error bit in the primary status register.
PI7C8154B sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154B forwards the bad parity with the data back to the initiator on the secondary bus. If
the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus,
the data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154B completes the transaction normally.
PI7C8154B returns to the initiator the data and parity that was received from the target. When the
initiator detects a parity error on this read data and is enabled to report it, the initiator asserts
PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility
for handling a parity error condition; therefore, when PI7C8154B detects PERR# asserted while
returning read data to the initiator, PI7C8154B does not take any further action and completes the
transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8154B detects a data parity error during a delayed write transaction, the initiator drives
data and data parity, and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8154B completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data,
byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When
PI7C8154B detects a parity error on the write data for the initial delayed write request transaction,
the following events occur:
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8154B asserts
TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested,
STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer,
PI7C8154B also asserts PERR#.
If the parity-error-response bit is not set, PI7C8154B returns a target retry. It queues the
transaction as usual. PI7C8154B does not assert PERR#. In this case, the initiator repeats the
transaction.
PI7C8154B sets the detected-parity-error bit in the status register corresponding to the initiator
bus, regardless of the state of the parity-error-response bit.
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent
delayed write transactions on the initiator bus, it is possible that the initiator’s re-attempts of the
write transaction may not match the original queued delayed write information contained in the
delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in
a system error (P_SERR# assertion).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
| PI7C9X20404GPBNBE | IC PCIE PACKET SWITCH 148LFBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。