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| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 84/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 71 of 114
JUNE 2008 REVISION 1.1
9.2
EEPROM MODE AT RESET
During a reset, the bridge will autoload information/data from the EEPROM if the automatic load
condition is met. The first offset in the EEPROM contains a signature. If the signature is
recognized, the autoload will initiate right after the reset.
During the autoload, the bridge will read sequential words from the EEPROM and write to the
appropriate registers. Before the bridge registers can be accessed through the host, the autoload
condition should be verified by reading bit[3] offset 54h (EEPROM Autoload Status). The host
access is allowed only after the status of this bit becomes '1' which signifies that the autoload
initialization sequence has completed successfully.
9.3
EEPROM DATA STRUCTURE
The bridge will access the EEPROM one WORD at a time. The bit order during the address phase
is reverse that of the data phase. The data order starts with the MSB to the LSB during the address
phase, but starts with the LSB to the MSB during the data phase.
9.4
EEPROM CONTENT
EEPROM BYTE
ADDRESS
CONFIGURATION
OFFSET
DESCRIPTION
00 – 01h
EEPROM SIGNATURE
Autoload will only proceed if it reads a value of 1516h on
the first word loaded.
02h
REGION ENABLE
Enables or disables certain regions of the PCI configuration
space from being loaded with contents in the EEPROM.
bit[0]: reserved
bit[4:1]: 0000 = stop autoload at offset 03h
0001 = stop autoload at offset 0Fh
0011 = stop autoload at offset 2Bh
other combinations are undefined
bit[7:5]: reserved
03h
ENABLE MISCELLANEOUS FUNCTIONS
bit[0]: ISA enable control bit write protect – When this it is
set, bridge will change bit[2] offset 3Eh into Read Only, and
the ISA enable feature will not be available.
04 – 05h
00 – 01h
Vendor ID
06 – 07h
02 – 03h
Device ID
08h
Reserved
09h
Class Code – low byte of Class Code register
0A – 0Bh
Class Code – upper bytes of Class Code register
0Ch
0Eh
Header Type
0Dh
0Fh
BIST
0E – 0Fh
Reserved
10 – 11h
42 – 43h
Arbiter Control Register
12h
48h
Memory Read Flow/Underflow Control
13h
4Ah
Upstream Memory Base and Limit Enable
14h
4Fh
Arbiter Pre-emption Control (only bit[31:28])
15 – 16h
58 – 59h
Upstream Memory Base Register
17 – 18h
5A – 5Bh
Upstream Memory Limit Register
19 – 1Ch
5C – 5Fh
Upstream Memory Base Upper 32-bit Register
1D – 20h
60 – 63h
Upstream Memory Limit Upper 32-bit Register
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| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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