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參數(shù)資料
| 型號： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 46/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 37 of 112
JUNE 2008 REVISION 1.1
target disconnect or a master latency timer expiration during 32-bit data transfers on the opposite
interface.
2.9.5
64-BIT TRANSACTIONS – SUPPORT DURING RESET
PI7C8154B checks P_REQ64# while P_RESET# is asserted to determine whether the 64-bit
extensions are connected. If P_REQ64# is HIGH, PI7C8154B knows that the 64-bit extension
signals are not connected so it always drives the 64-bit extension outputs to have valid logic levels
on the inputs. PI7C8154B will then treat all transactions on the primary as 32-bit. If P_REQ64# is
LOW, the 64-bit signals should be connected to pull-up resistors on the board and PI7C8154B does
not perform any input biasing. PI7C8154B can then treat memory write and prefetchable memory
read transactions as 64-bit transactions on the primary.
PI7C8154B always asserts S_REQ64# LOW during S_RESET# to indicate that the 64-bit
extension is supported on the secondary bus. Individual pull-up resistors must always be supplied
for S_AD[63:32], S_CBE[7:4], and S_PAR64.
2.10
TRANSACTION FLOW THROUGH
Transaction flow through refers to data being removed from the read/write buffers concurrently as
data is still being written to the buffer.
For reads, flow through occurs when the initiator repeats the delayed transaction while some read
data is in the buffer, but the transaction is still ongoing on the target bus. For read flow through to
occur, there can be no other reads or writes previously posted in the same direction.
For writes, flow through occurs when PI7C8154B is able to arbitrate for the target bus, initiate the
transaction and receive TRDY# from the target, while receiving data from the same transaction on
the initiator bus. Flow through can only occur if the writes that were previously posted in the same
direction are completed.
2.11
TRANSACTION TERMINATION
This section describes how PI7C8154B returns transaction termination conditions back to the
initiator.
The initiator can terminate transactions with one of the following types of termination:
Normal termination
Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data
phase, and de-asserts IRDYL at the end of the last data phase in conjunction with either TRDY# or
STOP# assertion from the target.
Master abort
A master abort occurs when no target response is detected. When the initiator does not detect a
DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates
the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME#
on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in
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