Advance Information Page 54 of 114 JUNE 2008 REVISION 1.1 abort. If parity error response bit i" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 65/114頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 54 of 114
JUNE 2008 REVISION 1.1
abort. If parity error response bit is not set, PI7C8154B proceeds normally and accepts
transaction if it is directed to or across PI7C8154B.
PI7C8154B sets the detected parity error bit in the secondary status register
PI7C8154B asserts P_SERR# and sets signaled system error bit in status register, if both of the
following conditions are met:
The SERR# enable bit is set in the command register
The parity error response bit is set in the bridge control register
5.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8154B attempts to pass the data parity condition from one
interface to the other unchanged, whenever possible, to allow the master and target devices to
handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that occurs
when a parity error is detected and the way in which the parity condition is forwarded across
PI7C8154B.
5.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION
SPACE
When PI7C8154B detects a data parity error during a Type 0 configuration write transaction to
PI7C8154B configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8154B asserts P_TRDY# and
writes the data to the configuration register. PI7C8154B also asserts P_PERR#. If the parity error
response bit is not set, PI7C8154B does not assert P_PERR#.
PI7C8154B sets the detected parity error bit in the status register, regardless of the state of the
parity error response bit.
5.2.2
READ TRANSACTIONS
When PI7C8154B detects a parity error during a read transaction, the target drives data and data
parity, and the initiator checks parity and conditionally asserts PERR#. For downstream
transactions, when PI7C8154B detects a read data parity error on the secondary bus, the following
events occur:
PI7C8154B asserts S_PERR# two cycles following the data transfer, if the secondary interface
parity error response bit is set in the bridge control register.
PI7C8154B sets the detected parity error bit in the secondary status register.
PI7C8154B sets the data parity detected bit in the secondary status register, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8154B forwards the bad parity with the data back to the initiator on the primary bus. If the
data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the
data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154B completes the transaction normally.
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