Advance Information Page 53 of 114 JUNE 2008 REVISION 1.1 The device signaling the interrupt pe" />
參數資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數： 64/114頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產品變化通告： Product Discontinuation Notice 22/Jan/2010
標準包裝： 27
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應商設備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 53 of 114
JUNE 2008 REVISION 1.1
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device before
accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are forwarded.
PI7C8154B does not have a hardware mechanism to guarantee data synchronization for posted
write transactions. Therefore, all posted write transactions must be followed by a read operation,
either from the device to the location just written (or some other location along the same path), or
from the device driver to one of the device registers.
5
ERROR HANDLING
PI7C8154B checks, forwards, and generates parity on both the primary and secondary interfaces.
To maintain transparency, PI7C8154B always tries to forward the existing parity condition on one
bus to the other bus, along with address and data. PI7C8154B always attempts to be transparent
when reporting errors, but this is not always possible, given the presence of posted data and
delayed transactions.
To support error reporting on the PCI bus, PI7C8154B implements the following:
PERR# and SERR# signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR# event disable register
This chapter provides detailed information about how PI7C8154B handles errors. It also describes
error status reporting and error operation disabling.
5.1
ADDRESS PARITY ERRORS
PI7C8154B checks address parity for all transactions on both buses, for all address and all bus
commands. When PI7C8154B detects an address parity error on the primary interface, the
following events occur:
If the parity error response bit is set in the command register, PI7C8154B does not claim the
transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If
parity error response bit is not set, PI7C8154B proceeds normally and accepts the transaction if
it is directed to or across PI7C8154B.
PI7C8154B sets the detected parity error bit in the status register.
PI7C8154B asserts P_SERR# and sets signaled system error bit in the status register, if both
the following conditions are met:
The SERR# enable bit is set in the command register
The parity error response bit is set in the command register
When PI7C8154B detects an address parity error on the secondary interface, the following events
occur:
If the parity error response bit is set in the bridge control register, PI7C8154B does not claim
the transaction with S_DEVSEL#; this may allow the transaction to terminate in a master
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