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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 102/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 88 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
4
Memory Read
Underflow
Control
R/W
0: Bridge will start returning memory read data to the source bus after the
2nd data is in the data buffer. If the data buffer is read as empty
(underflow), bridge will insert target wait states (up to 7 wait states) on
the source bus and prefetch more data in the data buffer. If there is no
further data coming into the data buffer and the number of wait states
reaches 7, the bridge will assert STOP# to disconnect the master and
terminate the transaction.
1: Bridge will not start returning memory read data to the source bus until
1 cache line of data is accumulated in the data buffer. If the data buffer is
read as empty (underflow), the bridge will stop prefetching at the
destination bus and signal a disconnect to the external master on the
source bus. The transaction entry and the associated data will be
discarded.
Reset to 0
15:5
Reserved
R/O
Returns 0 when read. Reset to 0.
14.1.33
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
16
Upstream (S to
P) Memory Base
and Limit Enable
R/W
0: Upstream memory range is the entire range except the downstream
memory channel
1: Upstream memory range is confined to the upstream Memory Base and
Limit
*see Offset 58h, 5Ch, and 60h for upstream memory range
31:17
Reserved
R/O
Returns 0 when read. Reset to 0.
14.1.34
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER –
OFFSET 4Ch
Bit
Function
Type
Description
31:28
Secondary bus
arbiter
preemption
contorl
R/W
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles after FRAME asserted
0001: Preemption enabled after 1 clock cycle after FRAME asserted
0010: Preemption enabled after 2 clock cycles after FRAME asserted
0011: Preemption enabled after 4 clock cycles after FRAME asserted
0100: Preemption enabled after 8 clock cycles after FRAME asserted
0101: Preemption enabled after 16 clock cycles after FRAME asserted
0110: Preemption enabled after 32 clock cycles after FRAME asserted
0111: Preemption enabled after 64 clock cycles after FRAME asserted
14.1.35
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch
Bit
Function
Type
Description
27:0
Hot Swap Switch
Time Slot
Register
R/W
Hot Swap switch time slot set to 0003A98h (15K PCI clocks).
Reset to 0003A98h.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面開(kāi)發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
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