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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠(chǎng)商： | Pericom |
| 文件頁(yè)數(shù)： | 86/114頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 73 of 114
JUNE 2008 REVISION 1.1
P_M66EN is HIGH and S_M66EN is LOW, the S_CLKOUT[9:0] outputs will be equal to half of
the ASYN_CLKIN. The PI7C8154B in asynchronous mode may run in the following frequencies:
Table 11-1 VALID ASYNCHRONOUS CLOCK FREQUENCIES
Primary (MHz)
Secondary (MHz)
25MHz to 66MHz
25MHz to 66MHz*
*Up to 80MHz on the PI7C8154B-80 only
12
PCI POWER MANAGEMENT
PI7C8154B incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.0. These features include:
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3HOT and D3COLD power management states
Support for D0, D1, D2, D3HOT, and D3COLD power management states for devices behind the
bridge
Support of the B2 secondary bus power state when in the D3HOT power management state
Table 12-1 shows the states and related actions that the bridge performs during power management
transitions. (No other transactions are permitted.)
Table 12-1 POWER MANAGEMENT TRANSITIONS
Current Status
Next State
Action
D0
D3COLD
Power has been removed from PI7C8154B. A power-up reset must be
performed to bring PI7C8154B to D0.
D0
D3HOT
If enabled to do so by the BPCCE pin, PI7C8154B will disable the
secondary clocks and drive them LOW.
D0
D2
Unimplemented. PI7C8154B will ignore the write to the power state bits.
Power state will remain at D0.
D0
D1
Unimplemented. PI7C8154B will ignore the write to the power state bits.
Power state will remain at D0.
D3HOT
D0
PI7C8154B enables secondary clock outputs and performs an internal
chip reset. Signal S_RST# will not be asserted. All registers will be
returned to the reset values and buffers will be cleared.
D3COLD
Power has been removed from PI7C8154B. A power-up reset must be
performed to bring PI7C8154B to D0.
D3COLD
D0
Power-up reset. PI7C8154B performs the standard power-up reset
functions as described in Section 11.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do
not pass through PCI-to-PCI bridges.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面開(kāi)發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
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