Advance Information Page 17 of 112 JUNE 2008 REVISION 1.1 1.2.4 SECONDARY BUS INTERFACE SIGNALS" />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁(yè)數(shù)： 24/114頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類(lèi)型： 表面貼裝
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 17 of 112
JUNE 2008 REVISION 1.1
1.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION
Name
Pin #
Type
Description
S_AD[63:32]
C20, A21, D20, C21, C23,
C22, D21, E20, D22, E21,
E23, F21, F23, F22, G20,
G22, G21, H23, H22, H21,
J23, J20, J22, K23, K22,
K21, L23, L21, L22, M22,
M23, M21
TS
Secondary Upper 32-bit Address/Data:
Multiplexed address and data bus. Address is
indicated by S_FRAME# assertion. Write data is
stable and valid when S_IRDY# is asserted and read
data is stable and valid when S_IRDY# is asserted.
Data is transferred on rising clock edges when both
S_IRDY# and S_TRDY# are asserted. During bus
idle, bridge drives S_AD to a valid logic level when
S_GNT# is asserted respectively.
S_CBE[7:4]
A19, C19, A20, D19
TS
Secondary Upper 32-bit Command/Byte
Enables: Multiplexed command field and byte
enable field. During address phase, the initiator
drives the transaction type on these pins. The
initiator then drives the byte enables during data
phases. During bus idle, bridge drives S_CBE[7:0]
to a valid logic level when the internal grant is
asserted.
S_PAR64
N21
TS
Secondary Upper 32-bit Parity: S_PAR64 carries
the even parity of S_AD[63:32] and S_CBE[7:4] for
both address and data phases. S_PAR64 is driven
by the initiator and is valid 1 cycle after the first
address phase when a dual address command is used
and S_REQ64# is asserted. S_PAR64 is valid 1
clock cycle after the second address phase of a dual
address transaction when S_REQ64# is asserted.
S_PAR64 is valid 1 cycle after valid data is driven
when both S_REQ64# and S_ACK64# are asserted
for that data phase. S_PAR64 is driven by the
device driving read or write data 1 cycle after the
S_AD lines are driven. S_PAR64 is tri-stated 1
cycle after the S_AD lines are tri-stated. Devices
receive data sample S_PAR64 as an input to check
for possible parity errors during 64-bit transactions.
When not driven, S_PAR64 is pulled up to a valid
logic level through external resistors.
S_REQ64#
B19
STS
Secondary 64-bit Transfer Request: S_REQ64#
is asserted by the initiator to indicate that the
initiator is requesting a 64-bit data transfer.
S_REQ64# has the same timing as S_FRAME#.
When S_REQ64# is asserted LOW during reset, a
64-bit data path is supported. When S_REQ64# is
HIGH during reset, bridge drives S_AD[63:32],
S_CBE[7:4], and S_PAR64 to valid logic levels.
When deasserting, S_REQ64# is driven to a
deasserted state for 1 cycle and then sustained by an
external pull-up resistor.
S_ACK64#
C18
STS
Secondary 64-bit Transfer Acknowledge:
S_ACK64# is asserted by the target only when
S_REQ64# is asserted by the initiator to indicate the
target’s ability to transfer data using 64 bits.
S_ACK64# has the same timing as S_DEVSEL#.
When deasserting, S_ACK64# is driven to a
deasserted state for 1 cycle and then is sustained by
an external pull-up resistor.
1.2.5
CLOCK SIGNALS
Name
Pin #
Type
Description
P_CLK
T3
I
Primary Clock Input: Provides timing for all
transactions on the primary interface.
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