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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 2/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 10 of 112
JUNE 2008 REVISION 1.1
LIST OF TABLES
TABLE 2-1 PCI TRANSACTIONS.......................................................................................................................23
TABLE 2-2 WRITE TRANSACTION FORWARDING.......................................................................................25
TABLE 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ............................................27
TABLE 2-4 READ PREFETCH ADDRESS BOUNDARIES ...............................................................................29
TABLE 2-5 READ TRANSACTION PREFETCHING.........................................................................................29
TABLE 2-6 DEVICE NUMBER TO IDSEL S_AD PIN MAPPING ....................................................................33
TABLE 2-7 DELAYED WRITE TARGET TERMINATION RESPONSE ..........................................................41
TABLE 2-8 RESPONSE TO POSTED WRITE TARGET TERMINATION .......................................................41
TABLE 2-9 RESPONSE TO DELAYED READ TARGET TERMINATION .....................................................42
TABLE 4-1 SUMMARY OF TRANSACTION ORDERING ................................................................................51
TABLE 5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT (BIT 31 OF OFFSET
04H) ..............................................................................................................................................................58
TABLE 5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT.........................58
TABLE 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (BIT 24 OF OFFSET 04H)
......................................................................................................................................................................59
TABLE 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT...........................59
TABLE 5-5 ASSERTION OF P_PERR# ...............................................................................................................60
TABLE 5-6 ASSERTION OF S_PERR# ...............................................................................................................60
TABLE 5-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS...........................................................61
TABLE 8-1 GPIO OPERATION............................................................................................................................69
TABLE 8-2 GPIO SERIAL DATA FORMAT.......................................................................................................69
TABLE 11-1 VALID ASYNCHRONOUS CLOCK FREQUENCIES ..................................................................73
TABLE 12-1 POWER MANAGEMENT TRANSITIONS....................................................................................73
TABLE 14-1 CONFIGURATION SPACE MAP...................................................................................................76
TABLE 16-1 TAP PINS .......................................................................................................................................103
TABLE 16-2 JTAG BOUNDARY REGISTER ORDER.....................................................................................105
LIST OF FIGURES
FIGURE 7-1 SECONDARY ARBITER EXAMPLE .............................................................................................66
FIGURE 16-1 TEST ACCESS PORT DIAGRAM...............................................................................................102
FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS..........................................................109
FIGURE 18-1 304-BALL PBGA PACKAGE OUTLINE ....................................................................................112
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