Advance Information Page 110 of 114 JUNE 2008 REVISION 1.1 66 MHz 33 MHz Symbol Parameter Min. " />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 14/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標準包裝： 27
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應商設備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 110 of 114
JUNE 2008 REVISION 1.1
66 MHz
33 MHz
Symbol
Parameter
Min.
Max.
Min.
Max
.
Units
Tsu
Input setup time to CLK – bused signals 1,2,3
3
-
7
-
Tsu(ptp)
Input setup time to CLK – point-to-point 1,2,3
5
-
10, 124
-
Th
Input signal hold time from CLK 1,2
0
-
0
-
Tval
CLK to signal valid delay – bused signals 1,2,3
2
6
2
11
Tval(ptp)
CLK to signal valid delay – point-to-point 1,2,3
2
6
2
12
Ton
Float to active delay 1,2
2
-
2
-
Toff
Active to float delay 1,2
-
14
-
28
ns
1. See Figure 17-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are
synchronized to S_CLKOUT.
3. Point-to-point signals are P_REQ#, S_REQ#[7:0], P_GNT#, S_GNT#[7:0], HSLED, HS_SW#,
HS_EN, and ENUM#. Bused signals are P_AD, P_BDE#, P_PAR, P_PERR#, P_SERR#,
P_FRAME#, P_IRDY#, P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, P_PAR64,
P_REQ64#, P_ACK64#, S_AD, S_CBE#, S_PAR, S_PERR#, S_SERR#, S_FRAME#,
S_IRDY#, S_TRDY#, S_LOCK#, S_DEVSEL#, S_STOP#, S_PA64, S_REQ64#, and
S_ACK64#.
4. REQ# signals have a setup of 10ns and GNT# signals have a setup of 12ns.
17.4
66MHZ PCI SIGNALING TIMING
Symbol
Parameter
Condition
Min.
Max.
Units
TSKEW
SKEW among S_CLKOUT[9:0]
0
0.250
TDELAY
DELAY between PCLK and S_CLKOUT[9:0]
20pF load
3.47
4.20
TCYCLE
P_CLK, S_CLKOUT[9:0] cycle time
15
30
THIGH
P_CLK, S_CLKOUT[9:0] HIGH time
6
TLOW
P_CLK, S_CLKOUT[9:0] LOW time
6
ns
17.5
33MHZ PCI SIGNALING TIMING
Symbol
Parameter
Condition
Min.
Max.
Units
TSKEW
SKEW among S_CLKOUT[9:0]
0
0.250
TDELAY
DELAY between PCLK and S_CLKOUT[9:0]
20pF load
3.47
4.20
TCYCLE
P_CLK, S_CLKOUT[9:0] cycle time
30
THIGH
P_CLK, S_CLKOUT[9:0] HIGH time
11
TLOW
P_CLK, S_CLKOUT[9:0] LOW time
11
ns
17.6
RESET TIMING
Symbol
Parameter
Min.
Max.
Units
TRST
P_RESET# active time after power stable
1
-
us
TRST-CLK
P_RESET# active time after P_CLK stable
100
-
us
TRST-OFF
P_RESET# active-to-output float delay
-
40
ns
TSRST
S_RESET# active after P_RESET# assertion
-
40
ns
TSRST-ON
S_RESET# active time after S_CLKIN stable
100
-
us
TDRST
S_RESET# deassertion after P_RESET# deassertion
20
25
cycles
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