Advance Information Page 13 of 112 JUNE 2008 REVISION 1.1 Name Pin # Type Description P_IRDY# A" />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁(yè)數(shù)： 20/114頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類(lèi)型： 表面貼裝
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 13 of 112
JUNE 2008 REVISION 1.1
Name
Pin #
Type
Description
P_IRDY#
AC5
STS
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it
is driven to a de-asserted state for one cycle.
P_TRDY#
AB5
STS
Primary TRDY (Active LOW). Driven by the
target of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated,
it is driven to a de-asserted state for one cycle.
P_DEVSEL#
AA6
STS
Primary Device Select (Active LOW). Asserted
by the target indicating that the device is accepting
the transaction. As a master, bridge waits for the
assertion of this signal within 5 cycles of
P_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a
de-asserted state for one cycle.
P_STOP#
AC6
STS
Primary STOP (Active LOW). Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
P_LOCK#
AB6
I
Primary LOCK (Active LOW). Asserted by an
initiator, one clock cycle after the first address phase
of a transaction, attempting to perform an operation
that may take more than one PCI transaction to
complete.
P_IDSEL
Y1
I
Primary ID Select. Used as a chip select line for
Type 0 configuration access to bridge configuration
space.
P_PERR#
AC7
STS
Primary Parity Error (Active LOW). Asserted
when a data parity error is detected for data received
on the primary interface. Before being tri-stated, it
is driven to a de-asserted state for one cycle.
P_SERR#
Y7
OD
Primary System Error (Active LOW). Can be
driven LOW by any device to indicate a system
error condition. Bridge drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
P_REQ#
U3
TS
Primary Request (Active LOW): This is asserted
by BRIDGE to indicate that it wants to start a
transaction on the primary bus. Bridge de-asserts
this pin for at least 2 PCI clock cycles before
asserting it again.
P_GNT#
R2
I
Primary Grant (Active LOW): When asserted,
PI7C8154B can access the primary bus. During idle
and P_GNT# asserted, bridge will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
P_RESET#
R3
I
Primary RESET (Active LOW): When
P_RESET# is active, all PCI signals should be
asynchronously tri-stated.
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