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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 48/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 39 of 112
JUNE 2008 REVISION 1.1
transaction with a master abort. This sets the received-master-abort bit in the status register
corresponding to the target bus.
For delayed read and write transactions, PI7C8154B is able to reflect the master abort condition
back to the initiator. When PI7C8154B detects a master abort in response to a delayed transaction,
and when the initiator repeats the transaction, PI7C8154B does not respond to the transaction with
DEVSEL#, which induces the master abort condition back to the initiator. The transaction is then
removed from the delayed transaction queue. When a master abort is received in response to a
posted write transaction, PI7C8154B discards the posted write data and makes no more attempts to
deliver the data. PI7C8154B sets the received-master-abort bit in the status register when the
master abort is received on the primary bus, or it sets the received master abort bit in the secondary
status register when the master abort is received on the secondary interface. When master abort is
detected in posted write transaction with both master-abort-mode bit (bit[5] of bridge control
register) and the SERR# enable bit (bit 8 of command register for secondary bus) are set,
PI7C8154B asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-
posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C8154B performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort received
bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
2.11.3
TARGET TERMINATION RECEIVED BY PI7C8154B
When PI7C8154B initiates a transaction on the target bus and the target responds with DEVSEL#,
the target can end the transaction with one of the following types
of termination:
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
PI7C8154B handles these terminations in different ways, depending on the type of transaction
being performed.
2.11.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8154B initiates a delayed write transaction, the type of target termination received from
the target can be passed back to the initiator.
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相關(guān)代理商/技術(shù)參數(shù) |
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| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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