- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1961 > PI7C8154BNAIE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠(chǎng)商： | Pericom |
| 文件頁(yè)數(shù)： | 23/114頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 16 of 112
JUNE 2008 REVISION 1.1
Name
Pin #
Type
Description
S_TRDY#
A10
STS
Secondary TRDY (Active LOW): Driven by the
target of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
S_DEVSEL#
B10
STS
Secondary Device Select (Active LOW): Asserted
by the target indicating that the device is accepting
the transaction. As a master, bridge waits for the
assertion of this signal within 5 cycles of
S_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a de-
asserted state for one cycle.
S_STOP#
C10
STS
Secondary STOP (Active LOW): Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
S_LOCK#
A11
STS
Secondary LOCK (Active LOW): Asserted by an
initiator, one clock cycle after the first address phase
of a transaction, when it is propagating a locked
transaction downstream. Bridge does not propagate
locked transactions upstream.
S_PERR#
C11
STS
Secondary Parity Error (Active LOW): Asserted
when a data parity error is detected for data received
on the secondary interface. Before being tri-stated,
it is driven to a de-asserted state for one cycle.
S_SERR#
B11
I
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system
error condition.
S_REQ#[8:0]
E1, E3, D2, D1, E4, D3, C2,
C1, D4
I
Secondary Request (Active LOW): This is
asserted by an external device to indicate that it
wants to start a transaction on the secondary bus.
The input is externally pulled up through a resistor
to VDD.
S_GNT#[8:0]
H1, G3, G2, G4, G1, F2, F1,
F3, E2
TS
Secondary Grant (Active LOW): PI7C8154B
asserts these pins to allow external masters to access
the secondary bus. Bridge de-asserts these pins for
at least 2 PCI clock cycles before asserting it again.
During idle and S_GNT# deasserted, PI7C8154B
will drive S_AD, S_CBE, and S_PAR.
S_RESET#
H2
O
Secondary RESET (Active LOW): Asserted when
any of the following conditions are met:
1.
Signal P_RESET# is asserted.
2.
Secondary reset bit in bridge control register in
configuration space is set.
3.
The chip reset bit in the chip control register in
configuration space is set.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, S_PAR, and
S_PAR64.
S_M66EN
A14
I/OD
Secondary Interface 66MHz Operation: This
input is used to specify if bridge is capable of
running at 66MHz on the secondary side. When
HIGH, the Secondary bus may run at 66MHz.
When LOW, the Secondary bus may only run at
33MHz. If P_M66EN is pulled LOW, the
S_M66EN is driven LOW.
S_CFN#
K1
I
Secondary Bus Central Function Control Pin:
When tied LOW, it enables the internal arbiter.
When tied HIGH, an external arbiter must be used.
S_REQ#[0] is reconfigured to be the secondary bus
grant input, and S_GNT#[0] is reconfigured to be
the secondary bus request output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
| PI7C9X20404GPBNBE | IC PCIE PACKET SWITCH 148LFBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面開(kāi)發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。