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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠(chǎng)商： | Pericom |
| 文件頁(yè)數(shù)： | 63/114頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 52 of 114
JUNE 2008 REVISION 1.1
Pass
Posted
Write
Delayed Read
Request
Delayed Write
Request
Delayed Read
Completion
Delayed Write
Completion
Delayed Write Request
No4
No
Yes
Delayed Read Completion
No3
Yes
No
Delayed Write Completion
Yes
No
Note: The superscript accompanying some of the table entries refers to any applicable ordering rule
listed in this section. Many entries are not governed by these ordering rules; therefore, the
implementation can choose whether or not the transactions pass each other.
The entries without superscripts reflect the PI7C8154B’s implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is followed
by an explanation, and the ordering rules are referred to by number in Table 4-1. These ordering
rules apply to posted write transactions, delayed write and read requests, and delayed write and
read completion transactions crossing PI7C8154B in the same direction. Note that delayed
completion transactions cross PI7C8154B in the direction opposite that of the corresponding
delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they were
received on the initiator bus. The subsequent posted write transaction can be setting a flag that
covers the data in the first posted write transaction; if the second transaction were to complete
before the first transaction, a device checking the flag could subsequently consume stale data.
2. A delayed read request traveling in the same direction as a previously queued posted write
transaction must push the posted write data ahead of it. The posted write transaction must complete
on the target bus before the delayed read request can be attempted on the target bus. The read
transaction can be to the same location as the write data, so if the read transaction were to pass the
write transaction, it would return stale data.
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling
in the same direction. In this case, the read data is traveling in the same direction as the write data,
and the initiator of the read transaction is on the same side of PI7C8154B as the target of the write
transaction. The posted write transaction must complete to the target before the read data is
returned
to the initiator. The read transaction can be a reading to a status register of the initiator of the
posted write data and therefore should not complete until the write transaction is complete.
4. Delayed write requests cannot pass previously queued posted write data. For posted memory
write transactions, the delayed write transaction can set a flag that covers the data in the posted
write transaction. If the delayed write request were to complete before the earlier posted write
transaction, a device checking the flag could subsequently consume stale data.
5. Posted write transactions must be given opportunities to pass delayed read and write requests
and completions. Otherwise, deadlocks may occur when some bridges which support delayed
transactions and other bridges which do not support delayed transactions are being used in the same
system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed
transaction queue.
4.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery. The
PCI Local Bus Specification, Revision 2.2, provides the following alternative methods for
synchronizing data and interrupts:
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| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面開(kāi)發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
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