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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 91/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 78 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
5
VGA Palette
Snoop Enable
R/W
Controls response to VGA compatible palette accesses
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and
3C9h (inclusive of ISA alias; AD[15:10] are not decoded and may be any
value)
6
Parity Error
Response
R/W
Controls response to parity errors
0: Bridge may ignore any parity errors that it detects and continue normal
operation
1: Bridge must take its normal action when a parity error is detected
Reset to 0
7
Wait Cycle
Control
R/O
Controls the ability to perform address / data stepping
0: disable address/data stepping (affects primary and secondary)
Reset to 0
8
P_SERR# enable
R/W
Controls the enable for the P_SERR# pin
0: disable the P_SERR# driver
1: enable the P_SERR# driver
Reset to 0
9
Fast Back-to-
Back Enable
R/W
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the primary interface.
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
15:10
Reserved
R/O
Returns 000000 when read
14.1.5
STATUS REGISTER – OFFEST 04h
Bit
Function
Type
Description
19:16
Reserved
R/O
Reset to 0
20
Capabilities List
R/O
Set to 1 to enable support for the capability list (offset 34h is the pointer
to the data structure)
Reset to 1
21
66MHz Capable
R/O
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
22
Reserved
R/O
Reset to 0
23
Fast Back-to-
Back Capable
R/O
Set to 1 to indicate bridge is capable of decoding fast back-to-back
transactions on the primary interface to different targets
Reset to 1
24
Data Parity Error
Detected
R/WC
0: No parity error detected on the primary interface (bridge is the primary
bus master)
1: Parity error detected on the primary interface (bridge is the primary
bus master)
Reset to 0
26:25
DEVSEL#
timing
R/O
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
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| PI7C8154EVB | 功能描述:界面開(kāi)發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
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