Advance Information Page 72 of 114 JUNE 2008 REVISION 1.1 EEPROM BYTE ADDRESS CONFIGURATION OFF" />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 85/114頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 72 of 114
JUNE 2008 REVISION 1.1
EEPROM BYTE
ADDRESS
CONFIGURATION
OFFSET
DESCRIPTION
21 – 22h
74 – 75h
Port Option Register
23 – 24h
80 – 81h
Secondary Master Timeout Counter
25 – 26h
82 – 83h
Primary Master Timeout Counter
27 – 28h
DE – DFh
Power Management Capabilities
29 – 2Ah
E0 – E1h
Power Management Control Status Register
2Bh
E3h
Power Management Data
2C – 3Fh
Reserved – MUST BE SET TO 0
10
VITAL PRODUCT DATA (VPD)
The bridge contains the Vital Product Data registers as specified in the PCI Local Bus
Specification, Revision 2.2. The bridge provides 192 bytes of storage in the EEPROM for the VPD
data starting at offset ECh of the configuration space.
11
CLOCKS
This chapter provides information about the clocks.
11.1
PRIMARY AND SECONDARY CLOCK INPUTS
PI7C8154B implements a primary clock input for the PCI interface. The primary interface is
synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to
the secondary clock input. The secondary clock operates at either the same frequency as the
primary clock, at half of the frequency of the primary clock, or can be derived from the secondary
clock input (ASYNC_CLKIN). PI7C8154B operates at a maximum frequency of 66 MHz. The
secondary interface may run up to 80MHz on the PI7C8154B-80.
11.2
SECONDARY CLOCK OUTPUTS
The bridge has 10 secondary clock outputs, S_CLKOUT[9:0], that can be used as clock inputs for
up to nine external secondary bus devices. In synchronous mode (ASYNC_SEL# = 1), the
S_CLKOUT[9:0] outputs are derived from P_CLK. The secondary clock edges are delayed from
P_CLK edges by a minimum of 0ns. In asynchronous mode (ASYNC_SEL# = 0), the
S_CLKOUT[9:0] outputs are derived from ASYNC_CLKIN. These are the rules for using
secondary clocks:
Each secondary clock output is limited to no more than one load
One of the secondary clock outputs must be used to feedback to S_CLKIN
11.3
ASYNCHRONOUS MODE
To set the PI7C8154B into asynchronous mode, ASYNC_SEL# must be set to 0. In asynchronous
mode, the S_CLKOUT[9:0] outputs will be derived from ASYNC_CLKIN. Clock division is still
functional based on the setting of the P_M66EN and S_M66EN pins. For example, when
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