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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 114/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 99 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
21:20
PI (Programming
Interface)
R/O
Read as 01 to indicate in addition to the features of Programming
Interface 0, Device Hiding, the DHA bit and the PIE bit are implemented
22
EXT (ENUM#
Status –
Extraction)
R/WC
0: ENUM# is not asserted
1: ENUM# is asserted
Reset to 0
23
INS (ENUM#
Status –
Insertion)
R/WC
0: ENUM# is not asserted
1: ENUM# is asserted
Reset to 0
31:24
Reserved
R/O
Returns 0 when read. Reset to 0
14.1.63
CAPABILITY ID REGISTER – OFFSET E8h
Bit
Function
Type
Description
7:0
Capability ID
R/O
Read as 03h to indicate these are VPD registers
14.1.64
NEXT POINTER REGISTER – OFFSET E8h
Bit
Function
Type
Description
15:8
Next Pointer
R/O
E4: HS_EN is 1
00: HS_EN is 0
14.1.65
VPD REGISTER – OFFSET E8h
Bit
Function
Type
Description
17:16
Reserved
R/O
Returns 0 when read. Reset to 0
23:18
VPD Address
R/W
VPD address for read / write cycle
30:24
Reserved
R/O
Returns 0 when read. Reset to 0
31
VPD Operation
R/W
Writing a 0 to this bit generates a read cycle from the EEPROM at the
VPD address specified in bits[7:2] of this register. This bit remains 0
until EEPROM cycle is finished, after which it will be set to 1. Data for
reads are available at offset ECh.
Writing a 1 to this bit generates a write cycle to the EEPROM at the VPD
address specified in bits[7:2] of this register. This bit remains at 1 until
EEPROM cycle is finished, after which it will be cleared to 0.
Reset to 0
14.1.66
VPD DATA REGISTER – OFFSET ECh
Bit
Function
Type
Description
31:0
VPD Data
R/W
VPD data (EEPROM data [address + 0x40].
The least significant byte of this register corresponds to the byte of VPD
at the address specified by the VPD address register. The data from or
written to this register uses the normal PCI byte transfer capabilities.
Reset to 0
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相關(guān)代理商/技術(shù)參數(shù) |
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| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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