Advance Information Page 59 of 114 JUNE 2008 REVISION 1.1 Secondary Detected Parity Error Bit T" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 70/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 59 of 114
JUNE 2008 REVISION 1.1
Secondary
Detected Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-3 shows setting data parity detected bit in the primary interface’s status register. This bit is
set under the following conditions:
PI7C8154B must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary interface,
must be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
Table 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (bit
24 of offset 04h)
Primary Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
0
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface.
This bit is set under the following conditions:
The PI7C8154B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT
Secondary
Detected Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / 1
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / 1
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