Advance Information Page 5 of 112 JUNE 2008 REVISION 1.1 TABLE OF CONTENTS LIST OF TABLES ....." />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 60/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 5 of 112
JUNE 2008 REVISION 1.1
TABLE OF CONTENTS
LIST OF TABLES ...............................................................................................................................................10
LIST OF FIGURES .............................................................................................................................................10
INTRODUCTION ...............................................................................................................................................11
1
SIGNAL DEFINITIONS ...........................................................................................................................12
1.1
SIGNAL TYPES ................................................................................................................................12
1.2
SIGNALS ...........................................................................................................................................12
1.2.1
PRIMARY BUS INTERFACE SIGNALS ........................................................................................12
1.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION ...................................................14
1.2.3
SECONDARY BUS INTERFACE SIGNALS ..................................................................................15
1.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION..................................................17
1.2.5
CLOCK SIGNALS..........................................................................................................................17
1.2.6
MISCELLANEOUS SIGNALS........................................................................................................18
1.2.7
GENERAL PURPOSE I/O INTERFACE SIGNALS.......................................................................19
1.2.8
JTAG BOUNDARY SCAN SIGNALS .............................................................................................19
1.2.9
POWER AND GROUND ...............................................................................................................19
1.3
PIN LIST ............................................................................................................................................20
2
SIGNAL DEFINITIONS ...........................................................................................................................23
2.1
TYPES OF TRANSACTIONS...........................................................................................................23
2.2
SINGLE ADDRESS PHASE .............................................................................................................24
2.3
DUAL ADDRESS PHASE ................................................................................................................24
2.4
DEVICE SELECT (DEVSEL#) GENERATION...............................................................................24
2.5
DATA PHASE ...................................................................................................................................24
2.6
WRITE TRANSACTIONS ................................................................................................................25
2.6.1
MEMORY WRITE TRANSACTIONS .............................................................................................25
2.6.2
MEMORY WRITE AND INVALIDATE..........................................................................................26
2.6.3
DELAYED WRITE TRANSACTIONS ............................................................................................26
2.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES......................................................................27
2.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS ....................................................................27
2.6.6
FAST BACK-TO-BACK TRANSACTIONS ....................................................................................28
2.7
READ TRANSACTIONS ..................................................................................................................28
2.7.1
PREFETCHABLE READ TRANSACTIONS ..................................................................................28
2.7.2
NON-PREFETCHABLE READ TRANSACTIONS.........................................................................28
2.7.3
READ PREFETCH ADDRESS BOUNDARIES .............................................................................29
2.7.4
DELAYED READ REQUESTS.......................................................................................................29
2.7.5
DELAYED READ COMPLETION ON TARGET BUS ..................................................................30
2.7.6
DELAYED READ COMPLETION ON INITIATOR BUS ..............................................................30
2.7.7
FAST BACK-TO-BACK TRANSACTIONS ....................................................................................31
2.8
CONFIGURATION TRANSACTIONS ............................................................................................31
2.8.1
TYPE 0 ACCESS TO PI7C8154A ..................................................................................................32
2.8.2
TYPE 1 TO TYPE 0 CONFIGURATION .......................................................................................32
2.8.3
TYPE 1 TO TYPE 1 FORWARDING .............................................................................................34
2.8.4
SPECIAL CYCLES.........................................................................................................................34
2.9
64-BIT OPERATION.........................................................................................................................35
2.9.1
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154B .............................................35
2.9.2
64-BIT TRANSACTIONS – ADDRESS PHASE .............................................................................35
2.9.3
64-BIT TRANSACTIONS – DATA PHASE ....................................................................................36
2.9.4
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154B ...............................................................36
2.9.5
64-BIT TRANSACTIONS – SUPPORT DURING RESET..............................................................37
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