Advance Information Page 77 of 114 JUNE 2008 REVISION 1.1 14.1.1 SIGNAL TYPES Signal Type Descr" />
參數(shù)資料
型號: PI7C8154BNAIE
廠商: Pericom
文件頁數(shù): 90/114頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標準包裝: 27
系列: *
應用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應商設備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 77 of 114
JUNE 2008 REVISION 1.1
14.1.1
SIGNAL TYPES
Signal Type
Description
R/O
Read Only
R/W
Read / Write
R/WC
Read / Write 1 to Clear
R/WR
Read / Write 1 to Reset (about 20 clocks)
R/WS
Read / Write 1 to Set
14.1.2
VENDOR ID REGISTER – OFFSET 00h
Bit
Function
Type
Description
15:0
Vendor ID
R/O
Identifies Pericom as vendor of this device. Hardwired as 12D8h.
14.1.3
DEVICE ID REGISTER – OFFSET 00h
Bit
Function
Type
Description
31:16
Device ID
R/O
Identifies this device as the PI7C8154B. Hardwired as 8154h.
14.1.4
COMMAND REGISTER – OFFSET 04h
Bit
Function
Type
Description
0
I/O Space Enable
R/W
Controls response to I/O access on the primary interface
0: ignore I/O transactions on the primary interface
1: enable response to I/O transactions on the primary interface
Reset to 0
1
Memory Space
Enable
R/W
Controls response to memory accesses on the primary interface
0: ignore memory transactions on the primary interface
1: enable response to memory transactions on the primary interface
Reset to 0
2
Bus Master
Enable
R/W
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary interface and
disable response to memory and I/O transactions on the secondary
interface
1: enables bridge to operate as a master on the primary interfaces for
memory and I/O transactions forwarded from the secondary interface
Reset to 0
3
Special Cycle
Enable
R/O
No special cycles defined.
Bit is defined as read only and returns 0 when read
4
Memory Write
And Invalidate
Enable
R/O
Bridge does not generate Memory Write and Invalidate except forwarding
a transaction for another master. Bit is implemented as read only and
returns 0 when read.
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