Advance Information Page 87 of 114 JUNE 2008 REVISION 1.1 Bit Function Type Description 26 Brok" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 101/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 87 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
26
Broken Master
Timeout Enable
R/W
0: Broken master timeout off. If a master receives its GNT# active but
does not initiate any transactions for more than 16 clocks, the arbiter will
consider the master as broken for only two clocks. The current GNT# will
be de-asserted if another master asserts its REQ# or automatic preemption
is on (bit[27] offset 40h); otherwise the current GNT# will be kept
asserted.
1: Broken master timeout on. If a master receives its GNT# active but
does not initiate any transactions for more than 16 clocks, the arbiter will
consider the master as broken and the REQ# of the current master will be
ignored for arbitration until de-assertion of its REQ#. The current GNT#
will be de-asserted if another master asserts its REQ# or automatic
preemption is on (bit[27] offset 40h); otherwise the current GNT# will be
kept asserted.
Reset to 0
27
Automatic
Preemption
Control
R/W
0: Automatic preemption off. If the preemption timer expires
(bit[31:28] offset 4Ch) and another master asserts REQ#, the GNT# of
the current master will be de-asserted and the GNT# of the next master
will be asserted. If no other master asserts REQ#, the current GNT# will
remain asserted.
1: Automatic preemption on. If the preemption timer expires
(bit[31:28] offset 4Ch), the GNT# to the current master will be de-
asserted for one clock. The same GNT# will be asserted again if no other
master asserts its REQ#. If another master asserts its REQ#, the arbiter
will generate a GNT# for the next master with the highest priority.
Reset to 0
31:28
Reserved
R/O
Returns 0000 when read. Reset to 0000.
14.1.32
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
0
Memory Read
Flow Through
Disable
R/W
Controls ability to do memory read flow through
0: Enable flow through during a memory read transaction
1: Disables flow through during a memory read transaction
Reset to 0
1
Park
R/W
Controls bus arbiter’s park function
0: Park to last master
1: Park to the bridge
Reset to 0
2
Downstream (P
to S) Memory
Read Dynamic
Prefetching
R/W
0: Enable downstream memory read prefetching dynamic control
1: Disable downstream memory read prefetching dynamic control
Reset to 0
3
Upstream (S to
P) Memory Read
Dynamic
Prefetching
R/W
0: Enable upstream memory read prefetching dynamic control
1: Disable upstream memory read prefetching dynamic control
Reset to 0
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