Advance Information Page 43 of 114 JUNE 2008 REVISION 1.1 FOR DELAYED READ TRANSACTIONS: The tr" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 53/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 43 of 114
JUNE 2008 REVISION 1.1
FOR DELAYED READ TRANSACTIONS:
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a posted write
transaction precedes it.
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been queued.
A locked sequence is being propagated across PI7C8154B, and the read transaction is not a
locked transaction.
PI7C78154B is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
FOR POSTED WRITE TRANSACTIONS:
The posted write data buffer does not have enough space for address and at least one DWORD
of write data.
A locked sequence is being propagated across PI7C8154B, and the write transaction is not a
locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat
the transaction with the same address and bus command as well as the data if it is a write
transaction, within the time frame specified by the master timeout value. Otherwise, the
transaction is discarded from the buffers.
2.11.4.2
TARGET DISCONNECT
PI7C8154B returns a target disconnect to an initiator when one of the following conditions is met:
PI7C8154B hits an internal address boundary.
PI7C8154B cannot accept any more write data.
PI7C8154B has no more read data to deliver.
See Section 2.6.4 for a description of write address boundaries, and Section 2.7.3 for a description
of read address boundaries.
2.11.4.3
TARGET ABORT
PI7C8154B returns a target abort to an initiator when one of the following conditions is met:
PI7C8154B is returning a target abort from the intended target.
When PI7C8154B returns a target abort to the initiator, it sets the signaled target abort bit in
the status register corresponding to the initiator interface.
3
ADDRESS DECODING
PI7C8154B uses three address ranges that control I/O and memory transaction forwarding. These
address ranges are defined by base and limit address registers in the configuration space. This
chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.
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