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參數(shù)資料
| 型號： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 92/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標準包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 79 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
27
Signaled Target
Abort
R/WC
0: Bridge does not signal target abort on the primary interface
1: Bridge signals target abort on the primary interface
Reset to 0
28
Received Target
Abort
R/WC
0: Bridge does not detect target abort on the primary interface
1: Bridge detects target abort on the primary interface
Reset to 0
29
Received Master
Abort
R/WC
0: Bridge does not detect master abort on the primary interface
1: Bridge detects master abort on the primary interface
Reset to 0
30
Signaled System
Error
R/WC
0: Bridge does not assert SERR# on the primary interface
1: Bridge asserts SERR# on the primary interface
Reset to 0
31
Detected Parity
Error
R/WC
0: Address of data parity error not detected by the bridge on the primary
interface
1: Address of data parity error detected by the bridge on the primary
interface
Reset to 0
14.1.6
REVISION ID REGISTER – OFFSET 08h
Bit
Function
Type
Description
7:0
Revision
R/O
Indicates revision number of device. Hardwired to 02h
14.1.7
CLASS CODE REGISTER – OFFSET 08h
Bit
Function
Type
Description
15:8
Programming
Interface
R/O
Read as 0 to indicate no programming interfaces have been defined for
PCI-to-PCI bridges
23:16
Sub-Class Code
R/O
Read as 04h to indicate device is PCI-to-PCI bridge
31:24
Base Class Code
R/O
Read as 06h to indicate device is a bridge device
14.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
7:0
Cache Line Size
R/W
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two are
valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h,
08h, and 10h are valid values).
Reset to 0
14.1.9
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
15:8
Primary Latency
timer
R/W
This register sets the value for the Master Latency Timer, which starts
counting when the master asserts FRAME#.
Reset to 0
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