Advance Information Page 95 of 114 JUNE 2008 REVISION 1.1 Bit Function Type Description 4 Secon" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 110/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標準包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 95 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
4
Secondary
Memory Write
Command Alias
Enable
R/W
0: exact matching for non-posted memory write retry cycles from initiator
on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry cycles
from initiator on the secondary interface
Reset to 0
5
Primary Memory
Read
Line/Multiple
Alias Enable
R/W
0: Exact matching for memory read line/multiple retry cycles from
initiator on the primary interface
1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory read
retry cycles from initiator on the primary interface
Reset to 1
6
Secondary
Memory Read
Line/Multiple
Alias Enable
R/W
0: Exact matching for memory read line/multiple retry cycles from
initiator on the secondary interface
1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory read
retry cycles from initiator on the secondary interface
Reset to 1
7
Primary Memory
Write and
Invalidate
Command Alias
Disable
R/W
0: When accepting MEMWI commands on primary, bridge converts
MEMWI to MEMW on destination bus
1: When accepting MEMWI commands on primary, bridge does not
convert MEMWI to MEMW on destination bus
Reset to 0
8
Secondary
Memory Write
and Invalidate
Command Alias
Disable
R/W
0: When accepting MEMWI commands on secondary, bridge converts
MEMWI to MEMW on destination bus
1: When accepting MEMWI commands on secondary, bridge does not
convert MEMWI to MEMW on destination bus
Reset to 0
9
Enable Long
Request
R/W
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
10
Enable
Secondary To
Hold Request
Longer
R/W
0: internal secondary master will release REQ# after FRAME# assertion
1: internal secondary master will hold REQ# until there is no transactions
pending in FIFO or until terminated by target
Reset to 1
11
Enable Primary
To Hold Request
Longer
R/W
0: internal Primary master will release REQ# after FRAME# assertion
1: internal Primary master will hold REQ# until there is no transactions
pending in FIFO or until terminated by target
Reset to 1
12
Ordering Rules
Control 1
R/W
0: Enable the out of order capability between two DTR requests from
two FIFO’s
1: Disable the out of order capability between two DTR requests from
two FIFO’s
Reset to 0
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