- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154BNAIE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 47/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 38 of 112
JUNE 2008 REVISION 1.1
the same cycle in which FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be
deasserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
Normal termination
TRDY# and DEVSEL# asserted in conjunction with FRAME# deasserted and IRDY# asserted.
Target retry
STOP# and DEVSEL# asserted with TRDY# deasserted during the first data phase. No data
transfers occur during the transaction. This transaction must be repeated.
Target disconnect with data transfer
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been
made, indicating that no more data transfers will be made during this transaction.
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to
complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction
before the target abort is signaled.
2.11.1
MASTER TERMINATION INITIATED BY PI7C8154B
PI7C8154B, as an initiator, uses normal termination if DEVSEL# is returned by target within five
clock cycles of PI7C8154B’s assertion of FRAME# on the target bus. As an initiator, PI7C8154B
terminates a transaction when the following conditions are met:
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data buffers
to the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the
master latency timer expires and the PI7C8154B’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
If PI7C8154B is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The
address of the transaction is updated to reflect the address of the current DWORD to be delivered.
If PI7C8154B is pre-fetching read data when it terminates the transaction because the master
latency timer expires, it does not repeat the transaction to obtain more data.
2.11.2
MASTER ABORT RECEIVED BY PI7C8154B
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by
the target within five clock cycles of the assertion of FRAME#, PI7C8154B terminates the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
| PI7C9X20404GPBNBE | IC PCIE PACKET SWITCH 148LFBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。