Advance Information Page 6 of 112 JUNE 2008 REVISION 1.1 2.10 TRANSACTION FLOW THROUGH ........" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 71/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標準包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 6 of 112
JUNE 2008 REVISION 1.1
2.10
TRANSACTION FLOW THROUGH ...............................................................................................37
2.11
TRANSACTION TERMINATION....................................................................................................37
2.11.1
MASTER TERMINATION INITIATED BY PI7C8154B............................................................38
2.11.2
MASTER ABORT RECEIVED BY PI7C8154B .........................................................................38
2.11.3
TARGET TERMINATION RECEIVED BY PI7C8154B............................................................39
2.11.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE ......................................................39
2.11.3.2
POSTED WRITE TARGET TERMINATION RESPONSE.........................................................41
2.11.3.3
DELAYED READ TARGET TERMINATION RESPONSE .......................................................41
2.11.4
TARGET TERMINATION INITIATED BY PI7C8154B ............................................................42
2.11.4.1
TARGET RETRY .......................................................................................................................42
2.11.4.2
TARGET DISCONNECT...........................................................................................................43
2.11.4.3
TARGET ABORT.......................................................................................................................43
3
ADDRESS DECODING ............................................................................................................................43
3.1
ADDRESS RANGES .........................................................................................................................44
3.2
I/O ADDRESS DECODING..............................................................................................................44
3.2.1
I/O BASE AND LIMIT ADDRESS REGISTER ..............................................................................45
3.2.2
ISA MODE .....................................................................................................................................45
3.3
MEMORY ADDRESS DECODING .................................................................................................46
3.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS..........................................46
3.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ...................................47
3.3.3
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS ..............................................48
3.4
VGA SUPPORT .................................................................................................................................49
3.4.1
VGA MODE ...................................................................................................................................49
3.4.2
VGA SNOOP MODE .....................................................................................................................49
4
TRANSACTION ORDERING .................................................................................................................50
4.1
TRANSACTIONS GOVERNED BY ORDERING RULES .............................................................50
4.2
GENERAL ORDERING GUIDELINES ...........................................................................................51
4.3
ORDERING RULES..........................................................................................................................51
4.4
DATA SYNCHRONIZATION ..........................................................................................................52
5
ERROR HANDLING ................................................................................................................................53
5.1
ADDRESS PARITY ERRORS ..........................................................................................................53
5.2
DATA PARITY ERRORS .................................................................................................................54
5.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE...........................54
5.2.2
READ TRANSACTIONS ................................................................................................................54
5.2.3
DELAYED WRITE TRANSACTIONS ............................................................................................55
5.2.4
POSTED WRITE TRANSACTIONS ...............................................................................................57
5.3
DATA PARITY ERROR REPORTING ............................................................................................58
5.4
SYSTEM ERROR (SERR#) REPORTING .......................................................................................61
6
EXCLUSIVE ACCESS..............................................................................................................................62
6.1
CONCURRENT LOCKS ...................................................................................................................62
6.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154B...........................................................62
6.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION.....................................................62
6.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................................64
6.3
ENDING EXCLUSIVE ACCESS......................................................................................................64
7
PCI BUS ARBITRATION.........................................................................................................................64
7.1
PRIMARY PCI BUS ARBITRATION ..............................................................................................65
7.2
SECONDARY PCI BUS ARBITRATION ........................................................................................65
7.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER......................................65
7.2.2
PREEMPTION...............................................................................................................................66
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