Advance Information Page 18 of 112 JUNE 2008 REVISION 1.1 Name Pin # Type Description S_CLKIN J" />
參數(shù)資料
型號： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 25/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產品變化通告： Product Discontinuation Notice 22/Jan/2010
標準包裝： 27
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應商設備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 18 of 112
JUNE 2008 REVISION 1.1
Name
Pin #
Type
Description
S_CLKIN
J4
I
Secondary Clock Input: Provides timing for all
transactions on the secondary interface.
S_CLKOUT[9:0]
P1, P2, P3, N1, N3, M2,
M1, M3, L3, L2
O
Secondary Clock Output: Provides secondary
clocks phase synchronous with the P_CLK.
When these clocks are used, one of the clock
outputs must be fed back to S_CLKIN. Unused
outputs may be disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins
and MSK_IN
3. Terminating them electrically.
ASYNC_SEL#
AB1
I
Asynchronous Mode Enable: Enables
asynchronous mode for the bridge.
0: Secondary bus clock outputs (S_CLKOUT[9:0])
will use the clock signal from ASYNC_CLKIN
input instead of the P_CLK.
1: Secondary bus clock outputs (S_CLKOUT[9:0])
will use the P_CLK input for synchronous
operation.
ASYNC_CLKIN
AB2
I
Asynchronous Mode Clock: External clock input
used to generate the secondary clock outputs
(S_CLKOUT[9:0]) when enabled by
ASYNC_SEL#
1.2.6
MISCELLANEOUS SIGNALS
Name
Pin #
Type
Description
MSK_IN
R21
I
Secondary Clock Disable Serial Input: This pin is
used by bridge to disable secondary clock outputs.
The serial stream is received by MSK_IN, starting
when P_RESET is detected deasserted and
S_RESET# is detected as being asserted. The serial
data is used for selectively disabling secondary
clock outputs and is shifted into the secondary clock
control configuration register. This pin can be tied
LOW to enable all secondary clock outputs or tied
HIGH to drive all the secondary clock outputs
HIGH.
P_VIO
R20
I
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus.
P_VIO must be tied to 3.3V only when all devices
on the primary bus use 3.3V signaling. Otherwise,
P_VIO is tied to 5V.
S_VIO
N22
I
Secondary I/O Voltage: This pin is used to
determine either 3.3V or 5V signaling on the
secondary bus. S_VIO must be tied to 3.3V only
when all devices on the secondary bus use 3.3V
signaling. Otherwise, S_VIO is tied to 5V.
BPCCE
R4
I
Bus/Power Clock Control Management Pin:
When this pin is tied HIGH and the bridge is placed
in the D2 or D3HOT power state, it enables the bridge
to place the secondary bus in the B2 power state.
The secondary clocks are disabled and driven to 0.
When this pin is tied LOW, there is no effect on the
secondary bus clocks when the bridge enters the D2
or D3HOT power state.
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