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| 型號： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 112/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標準包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 97 of 114
JUNE 2008 REVISION 1.1
14.1.53
CHASSIS NUMBER REGISTER – OFFSET B0h
Bit
Function
Type
Description
31:24
Chassis Number
R/W
Indicates chassis number
Reset to 0
14.1.54
CAPABILITY ID REGISTER – OFFSET DCh
Bit
Function
Type
Description
7:0
Enhanced
Capabilities ID
R/O
Read as 01h to indicate that these are power management enhanced
capability registers.
14.1.55
NEXT ITEM POINTER REGISTER – OFFSET DCh
Bit
Function
Type
Description
15:8
Next Item
Pointer
R/O
Read as B0h. Points to slot number register.
14.1.56
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh
Bit
Function
Type
Description
18:16
Power
Management
Revision
R/O
Read as 001 to indicate the device is compliant to Revision 1.0 of PCI
Power Management Interface Specifications.
19
PME# Clock
R/O
Read as 0 to indicate Bridge does not support the PME# pin.
20
Auxiliary Power
R/O
Read as 0 to indicate bridge does not support the PME# pin or an
auxiliary power source.
21
Device Specific
Initialization
R/O
Read as 0 to indicate bridge does not have device specific initialization
requirements.
24:22
Reserved
R/O
Read as 0
25
D1 Power State
Support
R/O
Read as 0 to indicate bridge does not support the D1 power management
state.
26
D2 Power State
Support
R/O
Read as 0 to indicate bridge does not support the D2 power management
state.
31:27
PME# Support
R/O
Read as 0 to indicate bridge does not support the PME# pin.
14.1.57
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
Function
Type
Description
1:0
Power State
R/W
Indicates the current power state of bridge. If an unimplemented power
state is written to this register, bridge completes the write transaction,
ignores the write data, and does not change the value of the field. Writing
a value of D0 when the previous state was D3 cause a chip reset without
asserting S_RESET#
00: D0 state
01: D1 state (supported if bit[25] offset DCh is HIGH)
10: D2 state (supported if bit[26] offset DCh is HIGH)
11: D3 state
Reset to 0
7:2
Reserved
R/O
Read as 0
8
PME_L Enable
R/O
Read as 0 as bridge does not support the PME# pin.
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