Advance Information Page 94 of 114 JUNE 2008 REVISION 1.1 14.1.46 P_SERR# STATUS REGISTER – OFF" />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁數(shù)： 109/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 94 of 114
JUNE 2008 REVISION 1.1
14.1.46
P_SERR# STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
16
Address Parity
Error
R/WC
1: Signal P_SERR# was asserted because an address parity error was
detected on P or S bus.
Reset to 0
17
Posted Write
Data Parity Error
R/WC
1: Signal P_SERR# was asserted because a posted write data parity error
was detected on the target bus.
Reset to 0
18
Posted Write
Non-delivery
R/WC
1: Signal P_SERR# was asserted because the bridge was unable to deliver
post memory write data to the target after 224 attempts.
Reset to 0
19
Target Abort
during Posted
Write
R/WC
1: Signal P_SERR# was asserted because the bridge received a target
abort when delivering post memory write data.
Reset to 0.
20
Master Abort
during Posted
Write
R/WC
1: Signal P_SERR# was asserted because the bridge received a master
abort when attempting to deliver post memory write data
Reset to 0.
21
Delayed Write
Non-delivery
R/WC
1: Signal P_SERR# was asserted because the bridge was unable to deliver
delayed write data after 224 attempts.
Reset to 0
22
Delayed Read –
No Data from
Target
R/WC
1: Signal P_SERR# was asserted because the bridge was unable to read
any data from the target after 224 attempts.
Reset to 0.
23
Delayed
Transaction
Master Timeout
R/WC
1: Signal P_SERR# was asserted because a master did not repeat a read or
write transaction before master timeout.
Reset to 0.
31:24
Reserved
R/O
Returns 0 when read. Reset to 0
14.1.47
PORT OPTION REGISTER – OFFSET 74h
Bit
Function
Type
Description
0
Reserved
R/O
Returns 0 when read. Reset to 0.
1
Primary Memory
Read Command
Alias Enable
R/W
0: exact matching for non-posted memory write retry cycles from initiator
on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry cycles
from the initiator on the primary interface
Reset to 1
2
Primary Memory
Write Command
Alias Enable
R/W
Reserved
Reset to 0
3
Secondary
Memory Read
Command Alias
Enable
R/W
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry cycles
from initiator on the secondary interface
Reset to 1
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