Advance Information Page 8 of 112 JUNE 2008 REVISION 1.1 14.1.26 CAPABILITY POINTER R" />
參數(shù)資料
型號(hào)： PI7C8154BNAIE
廠商： Pericom
文件頁(yè)數(shù)： 93/114頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類(lèi)型： 表面貼裝
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)當(dāng)前第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 8 of 112
JUNE 2008 REVISION 1.1
14.1.26
CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................84
14.1.27
INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................84
14.1.28
INTERRUPT PIN REGISTER – OFFSET 3Ch .........................................................................84
14.1.29
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................................84
14.1.30
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h................................................86
14.1.31
ARBITER CONTROL REGISTER – OFFSET 40h....................................................................86
14.1.32
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h.....................................................87
14.1.33
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h..............................................88
14.1.34
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch..........88
14.1.35
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch...............................................88
14.1.36
EEPROM AUTOLOAD CONTROL / STATUS REGISTER – OFFSET 50h .............................89
14.1.37
EEPROM ADDRESS / CONTROL REGISTER – OFFSET 54h ...............................................89
14.1.38
EEPROM DATA REGISTER – OFFSET 54h ...........................................................................89
14.1.39
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET 58h .....................90
14.1.40
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET 58h ....................90
14.1.41
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT REGISTER – OFFSET
5Ch
...................................................................................................................................................90
14.1.42
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT REGISTER – OFFSET
60h
...................................................................................................................................................90
14.1.43
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h.........................................................90
14.1.44
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ......................................................92
14.1.45
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h...............................................92
14.1.46
P_SERR# STATUS REGISTER – OFFSET 68h ........................................................................94
14.1.47
PORT OPTION REGISTER – OFFSET 74h .............................................................................94
14.1.48
SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h...........................96
14.1.49
PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h.................................96
14.1.50
CAPABILITY ID REGISTER – OFFSET B0h ...........................................................................96
14.1.51
NEXT POINTER REGISTER – OFFSET B0h...........................................................................96
14.1.52
SLOT NUMBER REGISTER – OFFSET B0h ...........................................................................96
14.1.53
CHASSIS NUMBER REGISTER – OFFSET B0h .....................................................................97
14.1.54
CAPABILITY ID REGISTER – OFFSET DCh..........................................................................97
14.1.55
NEXT ITEM POINTER REGISTER – OFFSET DCh ...............................................................97
14.1.56
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh .................................97
14.1.57
POWER MANAGEMENT DATA REGISTER – OFFSET E0h..................................................97
14.1.58
PPB SUPPORT EXTENSIONS REGISTER – OFFSET E0h ....................................................98
14.1.59
DATA REGISTER – OFFSET E0h............................................................................................98
14.1.60
CAPABILITY ID REGISTER – OFFSET E4h ...........................................................................98
14.1.61
NEXT POINTER REGISTER – OFFSET E4h...........................................................................98
14.1.62
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET E4h ........................................98
14.1.63
CAPABILITY ID REGISTER – OFFSET E8h ...........................................................................99
14.1.64
NEXT POINTER REGISTER – OFFSET E8h...........................................................................99
14.1.65
VPD REGISTER – OFFSET E8h ..............................................................................................99
14.1.66
VPD DATA REGISTER – OFFSET ECh ..................................................................................99
15
BRIDGE BEHAVIOR .............................................................................................................................100
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES...................................................................100
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ........................................100
15.2.1
MASTER ABORT ....................................................................................................................100
15.2.2
PARITY AND ERROR REPORTING ......................................................................................100
15.2.3
REPORTING PARITY ERRORS .............................................................................................101
15.2.4
SECONDARY IDSEL MAPPING............................................................................................101
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .........................................................................101
16.1
BOUNDARY SCAN ARCHITECTURE .........................................................................................101
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