參數資料
| 型號： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數： | 22/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標準包裝： | 27 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應商設備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 15 of 112
JUNE 2008 REVISION 1.1
Name
Pin #
Type
Description
P_REQ64#
AC14
STS
Primary 64-bit Transfer Request: P_REQ64# is
asserted by the initiator to indicate that the initiator
is requesting a 64-bit data transfer. P_REQ64# has
the same timing as P_FRAME#. When P_REQ64#
is asserted LOW during reset, a 64-bit data path is
supported. When P_REQ64# is HIGH during reset,
bridge drives P_AD[63:32], P_CBE[7:4], and
P_PAR64 to valid logic levels. When deasserting,
P_REQ64# is driven to a deasserted state for 1 cycle
and then sustained by an external pull-up resistor.
P_ACK64#
AB14
STS
Primary 64-bit Transfer Acknowledge:
P_ACK64# is asserted by the target only when
P_REQ64# is asserted by the initiator to indicate the
target’s ability to transfer data using 64 bits.
P_ACK64# has the same timing as P_DEVSEL#.
When deasserting, P_ACK64# is driven to a
deasserted state for 1 cycle and then is sustained by
an external pull-up resistor.
1.2.3
SECONDARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
S_AD[31:0]
C3, A3, B3, C4, A4, B4, C5,
B5, A6, A7, D7, B7, A8,
B8, C8, A9, C13, B13, A13,
D13, C14, B14, C15, B15,
C16, B16, C17, B17, D17,
A17, B18, A18
TS
Secondary Address/Data: Multiplexed address and
data bus. Address is indicated by S_FRAME#
assertion. Write data is stable and valid when
S_IRDY# is asserted and read data is stable and
valid when S_IRDY# is asserted. Data is
transferred on rising clock edges when both
S_IRDY# and S_TRDY# are asserted. During bus
idle, bridge drives S_AD[31:0] to a valid logic level
when S_GNT# is asserted respectively.
S_CBE[3:0]
C6, D9, C12, A15
TS
Secondary Command/Byte Enables: Multiplexed
command field and byte enable field. During
address phase, the initiator drives the transaction
type on these pins. The initiator then drives the byte
enables during data phases. During bus idle, bridge
drives S_CBE[3:0] to a valid logic level when the
internal grant is asserted.
S_PAR
B12
TS
Secondary Parity: S_PAR is an even parity of
S_AD[31:0] and S_CBE[3:0] (i.e. an even number
of 1’s). S_PAR is valid and stable one cycle after
the address phase (indicated by assertion of
S_FRAME#) for address parity. For write data
phases, S_PAR is valid one clock after S_IRDY# is
asserted. For read data phase, S_PAR is valid one
clock after S_TRDY# is asserted. Signal S_PAR is
tri-stated one cycle after the S_AD lines are tri-
stated. During bus idle, bridge drives S_PAR to a
valid logic level when the internal grant is asserted.
S_FRAME#
B9
STS
Secondary FRAME (Active LOW): Driven by the
initiator of a transaction to indicate the beginning
and duration of an access. The de-assertion of
S_FRAME# indicates the final data phase requested
by the initiator. Before being tri-stated, it is driven
to a de-asserted state for one cycle.
S_IRDY#
C9
STS
Secondary IRDY (Active LOW): Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it
is driven to a de-asserted state for one cycle.
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相關代理商/技術參數 |
參數描述 |
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| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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