Advance Information Page 56 of 114 JUNE 2008 REVISION 1.1 For downstream transactions, when PI7" />
參數(shù)資料
型號(hào): PI7C8154BNAIE
廠(chǎng)商: Pericom
文件頁(yè)數(shù): 67/114頁(yè)
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類(lèi)型: 表面貼裝
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)當(dāng)前第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 56 of 114
JUNE 2008 REVISION 1.1
For downstream transactions, when PI7C8154B is delivering data to the target on the secondary
bus and S_PERR# is asserted by the target, the following events occur:
PI7C8154B sets the secondary interface data parity detected bit in the secondary status
register, if the secondary parity error response bit is set in the bridge control register.
PI7C8154B captures the parity error condition to forward it back to the initiator on the primary
bus.
Similarly, for upstream transactions, when PI7C8154B is delivering data to the target on the
primary bus and P_PERR# is asserted by the target, the following events occur:
PI7C8154B sets the primary interface data-parity-detected bit in the status register, if the
primary parity-error-response bit is set in the command register.
PI7C8154B captures the parity error condition to forward it back to the initiator on the
secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the write
transaction with the same address, command, data, and byte enable bits as the delayed write
command that is at the head of the posted data queue. Note that the parity bit is not compared when
determining whether the transaction matches those in the delayed transaction queues.
Two cases must be considered:
When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction
and was not detected on the target bus.
When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the initiator bus
and PI7C8154B has write status to return, the following events occur:
PI7C8154B first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154B sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator
bus and PI7C8154B has write status to return, the following events occur:
PI7C8154B first asserts S_TRDY# and then asserts S_PERR# two cycles later; if the
secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch).
PI7C8154B sets the secondary interface parity-error-detected bit in the secondary status
register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target bus and
the parity error condition was not originally detected on the initiator bus, the following events
occur:
Bridge asserts P_PERR# two cycles after the data transfer, if the following are both true:
The parity-error-response bit is set in the command register of the primary interface
The parity-error-response bit is set in the bridge control register of the secondary interface
相關(guān)PDF資料
PDF描述
PI7C9X110BNBE IC PCIE TO PCI REV BRG 160LFBGA
PI7C9X130DNDE IC PCIE-PCIX BRIDGE 1PORT 256BGA
PI7C9X20303SLCFDE IC PCIE PACKET SWITCH 128LQFP
PI7C9X20303ULAZPE IC PCIE PACKET SWITCH 132TQFN
PI7C9X20404GPBNBE IC PCIE PACKET SWITCH 148LFBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8154EVB 功能描述:界面開(kāi)發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
PI7C8154NA-33 制造商:PERICOM 功能描述:
PI7C81552 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C81552A 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C9X110 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge